지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.4
- 발행연도
- 2021.8
- 수록면
- 255 - 262 (8page)
- DOI
- 10.5573/JSTS.2021.21.4.255
이용수
초록· 키워드
오류제보하기
This work proposes two versions of a 12 b 100 MS/s successive-approximation register (SAR) ADC based on a non-binary C-R hybrid DAC. The proposed DAC applies a non-binary weighted capacitor array to the 7 MSBs to meet the settling requirement of the DAC output and determines the remaining 5 LSBs using the reference voltages generated from a simple resistor string to reduce the DAC area significantly. The Version 1 ADC in a 28 ㎚ CMOS adopts a synchronous SAR logic and a comparator with a tail capacitor and a reset switch to minimize power consumption. The Version 2 ADC in a 0.18 ㎛ CMOS employs an asynchronous SAR logic with simple meta-stability correction logic to achieve high-speed operation. The Version 1 ADC which has an active die area of 0.042 ㎟ shows a maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 62.3 and 77.3 ㏈, respectively, consuming 1.3 ㎽ with a 1.0 V supply voltage. The Version 2 ADC is based on a similar analog circuit topology, showing a maximum SNDR and SFDR of 60.1 and 73.5 ㏈, respectively, with an active die area of 0.30 ㎟, operating at a 1.8 V supply voltage.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED SAR ADC TOPOLOGY
Ⅲ. CIRCUIT DESCRIPTION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
J. S. Park, T. J. An, G. C. Ahn, and S. H. Lee, “A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 7, pp. 1119-1123, July, 2019.
G. Misra, A. Agarwal, S. Misra and K. Agarwal, "Device to device millimeter wave communication in 5G wireless cellular networks (A next generation promising wireless cellular technology)," International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), pp. 89-93 , Oct., 2016.
H. Kim et al., "A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs," IEEE J. of Solid-State Circuits, vol. 51, no. 10, pp. 2262-2273, Oct., 2016.
S. Wong, U. Chio, Y. Zhu, S. Sin, S. U and R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC," IEEE J. of Solid-State Circuits, vol. 48, no. 8, pp. 1783-1794, Aug., 2013.
Y. Liang, R. Ding and Z. Zhu, "A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals," IEEE Sensors Journal, vol. 18, no. 17, pp. 7130-7140, Sept., 2018.
G. Misra, A. Agarwal, S. Misra and K. Agarwal, "Device to device millimeter wave communication in 5G wireless cellular networks (A next generation promising wireless cellular technology)," International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), pp. 89-93 , Oct., 2016.
H. Kim et al., "A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs," IEEE J. of Solid-State Circuits, vol. 51, no. 10, pp. 2262-2273, Oct., 2016.
S. Wong, U. Chio, Y. Zhu, S. Sin, S. U and R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC," IEEE J. of Solid-State Circuits, vol. 48, no. 8, pp. 1783-1794, Aug., 2013.
Y. Liang, R. Ding and Z. Zhu, "A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals," IEEE Sensors Journal, vol. 18, no. 17, pp. 7130-7140, Sept., 2018.
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
직렬 커패시터 D/A 변환기를 갖는 저전력 축차 비교형 A/D 변환기
전기학회논문지
2019 .01
-
An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2023 .04
-
Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .12
-
저누설 샘플링 스위치를 이용한 RC hybrid DAC 구조의 100 kS/s 12-bit SAR ADC
대한전자공학회 학술대회
2024 .11
-
A 4b/cycle Flash-assisted SAR ADC with Comparator Speed-boosting Technique
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2018 .04
-
SAR ADC with Split-Capacitor Array DAC based on Optimally Tunable Foreground-Calibration
대한전자공학회 학술대회
2021 .11
-
C-DAC Array내 소자정합특성을 향상시킨 10비트 SAR ADC 설계
한국통신학회 학술대회논문집
2015 .06
-
Auto-Zero Comparator를 이용한 RC hybrid DAC 구조의 12-bit SAR ADC
대한전자공학회 학술대회
2022 .06
-
Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System
IEIE Transactions on Smart Processing & Computing
2015 .06
-
A 10-bit 10MS/s differential straightforward SAR ADC
IEIE Transactions on Smart Processing & Computing
2015 .06
-
C-DAC Array내 선형성을 향상시킨 10비트 CMOS SAR ADC 설계
전자공학회논문지
2017 .02
-
A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .10
-
A 6 bits 10 MS/s Asynchronous Loop-Unrolled SAR ADC
대한전자공학회 학술대회
2024 .06
-
C-DAC 비트 스위치에 다른 샘플링 시간을 인가하는 12-bit, 10-Msps SAR A/D 변환기 설계
전기전자학회논문지
2020 .12
-
A 2 GS/s, 6-bit DAC for UWB Applications In 0.18 ㎛ CMOS Technology
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2019 .12
-
Digital Error Correction for a 10-Bit Straightforward SAR ADC
IEIE Transactions on Smart Processing & Computing
2015 .02
-
An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .08
-
상위 6비트를 공유하는 12 비트 SAR A/D 변환기
전기전자학회논문지
2018 .12
-
VCM-based Switching기법을 이용한 RC hybrid DAC구조의 1 MS/s 10-bit SAR ADC
대한전자공학회 학술대회
2024 .11
이 논문의 저자 정보
최근 본 자료
댓글(0)
0