지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.6
- 발행연도
- 2019.12
- 수록면
- 517 - 526 (10page)
- DOI
- 10.5573/JSTS.2019.19.6.517
이용수
초록· 키워드
오류제보하기
To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 ㎜ CMOS technology and the area is 975 ㎛´ 775 ㎛. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 ㎓, the DAC can achieve a SFDR of 51 ㏈ for input signal of 6㎒, and a SFDR of 32.4 ㏈ for Nyquist input while the power consumption is 79 ㎽.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DAC STRUCTURE AND KEY BUILDING BLOCKS
Ⅲ. MEASUREMENT RESULTS
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
Wu, X., Palmers, P., Steyaert, M. S. J.. “A 130nm CMOS 6bit full Nyquist 3GS/s DAC,” IEEE Journal of Solid-State Circuits, Vol. 43, pp. 2396- 2408, 2008.
Greshishchev, Y.M., Pollex, D., Wang, S.C., Besson, M., Flemeke, P., Szilagyi, S., Aguirre, J., Falt, C., Hamida, N.B., Gibbins, R., Schvan, P.. “A 56GS/s 6b DAC in 65nm CMOS with 256 6b memory,” 2011 IEEE International Solid-State Circuits Conference, pp. 194-196, 2011.
Nagatani, M., Nosaka, H., Sano, K., Murata, K., Kurishima, K., Ida, M.. “A 60-GS/s 6bit DAC in 0.5mm InP HBT Technology for optical communication systems,” 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 1-4, 2011.
Kwon, Y. G., Lee, S. H., Jeon, Y. D., Kwon, J. K.. “A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme,” 2010 International SoC Design Conference, pp.198-200, 2010.
Chen, R. L., Chang, S. J.. “A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications,” IEEE Transactions on Circuit And Systems?II: Express Briefs, vol.59, pp.746-750, 2012.
Greshishchev, Y.M., Pollex, D., Wang, S.C., Besson, M., Flemeke, P., Szilagyi, S., Aguirre, J., Falt, C., Hamida, N.B., Gibbins, R., Schvan, P.. “A 56GS/s 6b DAC in 65nm CMOS with 256 6b memory,” 2011 IEEE International Solid-State Circuits Conference, pp. 194-196, 2011.
Nagatani, M., Nosaka, H., Sano, K., Murata, K., Kurishima, K., Ida, M.. “A 60-GS/s 6bit DAC in 0.5mm InP HBT Technology for optical communication systems,” 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 1-4, 2011.
Kwon, Y. G., Lee, S. H., Jeon, Y. D., Kwon, J. K.. “A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme,” 2010 International SoC Design Conference, pp.198-200, 2010.
Chen, R. L., Chang, S. J.. “A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications,” IEEE Transactions on Circuit And Systems?II: Express Briefs, vol.59, pp.746-750, 2012.
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