지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.2
- 발행연도
- 2023.4
- 수록면
- 118 - 127 (10page)
- DOI
- 10.5573/JSTS.2023.23.2.118
이용수
초록· 키워드
오류제보하기
This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm². The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively.
목차
Abstract
I. INTRODUCTION
II. PROPOSED SAR ADC ARCHITECTURE
III. CIRCUIT IMPLEMENTATION
IV. MEASUREMENT RESULTS
V. CONCLUSION
REFERENCES
참고문헌 (24)
참고문헌 신청
K. Yoshioka et al., "A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique," IEEE International Solid-State Circuits Conference (ISSCC), pp. 478-479, Feb., 2017.
J. Park, T. An, G. Ahn, and S. Lee, "A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 7, pp. 1119-1123, Jul., 2019.
B. Verbruggen, M. Iriguchi, and J. Craninckx, "A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2880-2887, Dec., 2012.
S. Wong, U. Chio, Y. Zhu, S. Sin, S. U, and R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC," IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1783-1794, Aug., 2013.
C. Liu, C. Kuo, and Y. Lin, "A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS," IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, Nov., 2015.
J. Park, T. An, G. Ahn, and S. Lee, "A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 7, pp. 1119-1123, Jul., 2019.
B. Verbruggen, M. Iriguchi, and J. Craninckx, "A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2880-2887, Dec., 2012.
S. Wong, U. Chio, Y. Zhu, S. Sin, S. U, and R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC," IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1783-1794, Aug., 2013.
C. Liu, C. Kuo, and Y. Lin, "A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS," IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, Nov., 2015.
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System
IEIE Transactions on Smart Processing & Computing
2015 .06
-
A 87.5-dB-SNDR Residue-integrated SAR ADC with a Digital-domain Capacitor Mismatch Calibration
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2021 .04
-
A 10-bit 10MS/s differential straightforward SAR ADC
IEIE Transactions on Smart Processing & Computing
2015 .06
-
Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2021 .10
-
A 4b/cycle Flash-assisted SAR ADC with Comparator Speed-boosting Technique
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2018 .04
-
에너지 소모량과 면적을 개선한 하이브리드 SAR ADC
한국전자파학회논문지
2021 .09
-
저전력 37uW 10-bit 모노토닉 축차비교형 아날로그 디지털 변환기
대한전자공학회 학술대회
2023 .06
-
An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .08
-
A 6 bits 10 MS/s Asynchronous Loop-Unrolled SAR ADC
대한전자공학회 학술대회
2024 .06
-
직렬 커패시터 D/A 변환기를 갖는 저전력 축차 비교형 A/D 변환기
전기학회논문지
2019 .01
-
고속동작과 정밀도 향상을 위해 Digital Error Correction을 이용한 10비트 100MS/s Non-binary SAR ADC
대한전자공학회 학술대회
2024 .11
-
내장 필터를 갖는 15b 고해상도 혼합형 A/D 변환기
센서학회지
2017 .01
-
소자 부정합에 덜 민감한 12비트 60MS/s 0.18um CMOS Flash-SAR ADC
전자공학회논문지
2016 .07
-
Digital Error Correction for a 10-Bit Straightforward SAR ADC
IEIE Transactions on Smart Processing & Computing
2015 .02
-
A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .12
-
고해상도 저전력 센서 시스템을 위한 아날로그-디지털 변환기의 구조 개선
전기전자학회논문지
2018 .06
-
Auto Zero Calibration 기법을 적용한 8-bit, 49.98dB SNDR SAR ADC 설계
대한전자공학회 학술대회
2024 .11
-
오버샘플링과 CIC 필터를 이용한 14-bit 1-kS/s SAR ADC
한국정보기술학회논문지
2024 .10
-
A Review of Noise Reduction Techniques in Noise-shaping SAR ADCs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .12
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2023-569-001465567