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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.4
- 발행연도
- 2022.8
- 수록면
- 205 - 215 (11page)
- DOI
- 10.5573/JSTS.2022.22.4.205
이용수
초록· 키워드
오류제보하기
A second-order noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for sensor interface applications. It consists of a capacitor-resistor hybrid digital-to-analog-converter (C-R DAC) with 10-bit resolution, a comparator with three inputs, a SAR logic, and a second passive integrator using two differential capacitors. The use of a C-R DAC and two differential capacitors reduces the capacitor area of the conventional NS SAR ADC by 86.25%. Voltage gain calibration for the three-input comparator is proposed to maximize the performance of the NS SAR ADC. The proposed second-order NS ADC is designed using a 180-nm CMOS process with a supply of 1.8 V. The proposed second-order NS SAR ADC with an over sampling ratio of 8 has a SNDR of 80.18 dB and an ENOB of 13.03 bits. Its area and power consumption are 0.165 ㎟ and 248 μW, respectively.
목차
Abstract
I. INTRODUCTION
II. BEHAVIORAL MODEL OF SECOND-ORDER NOISE SHAPING SAR ADC
III. DESIGN OF SECOND-ORDER NOISE SHAPING SAR ADC
IV. CHIP IMPLEMENTATION ANDMEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (15)
참고문헌 신청
C.-C. Liu and M-C Huang, “A 0.46mW 5MHz-BW 79.7dB-SNDR Noise-Shaping SAR ADC with Dynamic-Amplifier-Based FIR-IIR Filter,” IEEE International Solid-State Circuits Conference, pp. 466-467, Feb. 2017.
S. Li, B. Qiao, M. Gandara, D. Z. Pan, and N. Sun, “A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018.
S. Karmakar, B. Gònen, F. Sebastiano, R. Van Veldhoven, and K. A. A. Makinwa, “A 280 μW dynamic-zoom ADC with 120 dB DR and 118 dB SNDR in 1 kHz BW,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3497-3507, Dec. 2018.
Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, “An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016.
M. Miyahara and A. Matsuzawa, “An 84 dB dynamic range 62.5-625 kHz bandwidth clockscalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier,” IEEE Custom Integrated Circuits Conference, pp. 1-4, Apr. 2017.
S. Li, B. Qiao, M. Gandara, D. Z. Pan, and N. Sun, “A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3484-3496, Dec. 2018.
S. Karmakar, B. Gònen, F. Sebastiano, R. Van Veldhoven, and K. A. A. Makinwa, “A 280 μW dynamic-zoom ADC with 120 dB DR and 118 dB SNDR in 1 kHz BW,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3497-3507, Dec. 2018.
Y.-S. Shu, L.-T. Kuo, and T.-Y. Lo, “An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2928-2940, Dec. 2016.
M. Miyahara and A. Matsuzawa, “An 84 dB dynamic range 62.5-625 kHz bandwidth clockscalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier,” IEEE Custom Integrated Circuits Conference, pp. 1-4, Apr. 2017.
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