지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.5
- 발행연도
- 2017.10
- 수록면
- 636 - 647 (12page)
- DOI
- 10.5573/JSTS.2017.17.5.636
이용수
초록· 키워드
오류제보하기
This work proposes a two-channel T-I 10b 160 MS/s asynchronous pipelined-SAR ADC minimizing offset and gain mismatches between channels without any calibration. Each channel of the proposed ADC is based on a two-stage pipelined-SAR topology, where the first and second stage determines 4b and 7b, respectively, for high conversion rate and low power. An asynchronous SAR algorithm removes on-chip high-speed clock generators for SAR operation, while a simple detection circuit solves a meta-stability problem of the comparator commonly observed in asynchronous SAR ADCs. Analog circuits such as comparators and residue amplifiers are shared to capacity between two channels to reduce various channel mismatches limiting the linearity of the T-I ADC. Three separate reference voltage drivers for two SAR ADCs and a residue amplifier prevent lots of undesirable disturbance among reference voltages due to each different switching operation. The prototype ADC in a 28 nm CMOS process demonstrates a measured differential and integral nonlinearity within 0.71 LSB and 0.70 LSB at 10b, respectively, with a maximum signal-to-noise-anddistortion ratio and a spurious-free dynamic range of 51.43 dB and 62.01 dB at 160 MS/s, respectively. The proposed ADC occupies an active die area of 0.23 ㎟ and consumes 3.5 mW at a 1.0 V supply voltage.
목차
Abstract
I. INTRODUCTION
II. PROPOSED TWO-CHANNEL T-I PIPELINEDSAR ADC
III. DESIGN ISSUES TO REDUCE CHANNEL MISMATCH AND CIRCUIT NOISE
IV. CIRCUIT IMPLEMENTATION
V. PROTOTYPE ADC MEASUREMENTS
VI. CONCLUSION
REFERENCES
참고문헌 (25)
참고문헌 신청
H. Kim, T. An, S. Myung, and S. Lee, Timeinterleaved and circuit-shared dual-channel 10 b 200 MS/s 0.18 μm CMOS analog-to-digital convertor, IEEE Trans. Very Large Integration System, vol. 21, no. 12, pp.2206-2213, Dec., 2013.
C. Tseng, Y. Hsieh, C. Yang and H. Chen, A 10- bit 200 MS/s capacitor-sharing pipeline ADC, IEEE Trans. Circuits Syst. I, vol. 60, no. 11, pp.2902-2910, Nov., 2013.
Y. Kim and S. Lee, A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, pp.75-87, Jan., 2012.
S. Lee, Y. Jeon, J. Kwon, and J. Kim, A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS pipeline ADC for flat panel display applications, IEEE J. Solid- States Circuits, vol. 42, no. 12, pp.2688-2695, Dec., 2007.
K. Hseush, Y. Chou, Y. Tu, Y. Chen, Y. Yang, and H. Li, “A 1V 11b 200MS/s pipelined ADC with digital background calibration in 65nm CMOS,” in ISSCC Dig. Tech Papers, pp. 546-547, Feb., 2008.
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