지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제11권 제1호
- 발행연도
- 2010.1
- 수록면
- 15 - 19 (5page)
이용수
초록· 키워드
오류제보하기
In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a 0.35 µm standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and 1.5 µm. The drain current ( ), transconductance ( ), substrate current ( ), drain to source leakage current ( ), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved and characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and characteristics.
목차
등록된 정보가 없습니다.
참고문헌 (10)
참고문헌 신청
/ 2003 / MEDICI User's Manual / Synopsys, Inc.
B. Cheng / 1998 / / Pro-ceedings of the 28th european solid-state device research conference : 520 ~
B. Cheng / 1999 / / IEEE Electron Device Lett. 20 : 538 ~
D. G. Borse / 2002 / / IEEE Trans. Electron Devices 49 : 1077 ~
D. V. Kumar / 2005 / / IEEE Trans. Elec-tron Devices 52 : 1603 ~
B. Cheng / 1998 / / Pro-ceedings of the 28th european solid-state device research conference : 520 ~
B. Cheng / 1999 / / IEEE Electron Device Lett. 20 : 538 ~
D. G. Borse / 2002 / / IEEE Trans. Electron Devices 49 : 1077 ~
D. V. Kumar / 2005 / / IEEE Trans. Elec-tron Devices 52 : 1603 ~
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
비대칭 채널을 갖는 고전압 Extended-Drain MOSFET의 스위칭 및 아날로그 특성
대한전자공학회 학술대회
2012 .06
-
Preparation of Epoxy/Organoclay Nanocomposites for Electrical Insulating Material Using an Ultrasonicator
Transactions on Electrical and Electronic Materials
2011 .01
-
Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 ㎚ Single/Double Gate SOI MOSFETs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2008 .06
-
Threshold Voltage Control through Layer Doping of Double Gate MOSFETs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2010 .09
-
3차원 구조 소자에서의 doping profile에 따른 전류 특성 분석
대한전자공학회 학술대회
2006 .06
-
Effects of Hafnium Oxide on Surface Potential and Drain Current Models for Subthreshold Short Channel Metal–Oxide–Semiconductor-Field-Effect-Transistor
Transactions on Electrical and Electronic Materials
2020 .01
-
Novel properties of erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2004 .06
-
작동중인 모스 전계 효과 트랜지스터 단면에서의 상대온도 및 전위 분포 측정
대한기계학회 논문집 B권
2003 .07
-
Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance
Transactions on Electrical and Electronic Materials
2020 .01
-
Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2007 .06
-
2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOI MOSFETs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2009 .06
-
Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2006 .03
-
Fabrication Process of Cone SONOS Memory Structure
ICEIC : International Conference on Electronics, Informations and Communications
2008 .06
-
DG-SET 성능 향상을 위한 공정 방법
대한전자공학회 학술대회
2008 .11
-
작동중인 모스 전계 효과 트랜지스터 단면에서의 온도 분포 측정
대한기계학회 춘추학술대회
2002 .05
-
Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2015 .12
-
드레인 전압 종속 게이트-벌크 MOSFET 캐패시턴스 추출 데이터를 사용한 측면 채널 도핑 분포 측정
전자공학회논문지-SD
2011 .10
-
Analysis on Characteristics of Tunnel Field Effect Transistor with Elevated Drain by Changing Drain Underlap Length
대한전자공학회 학술대회
2019 .06
-
Research for Hot Carrier Degradation in N-Type Bulk FinFETs
전기전자재료학회논문지
2020 .01
-
Avalanche Hot Source Method for Separated Extraction of Parasitic Source and Drain Resistances in Single Metal-Oxide-Semiconductor Field Effect Transistors
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2012 .03
이 논문의 저자 정보
최근 본 자료
댓글(0)
0