지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.7 No.4
- 발행연도
- 2021.10
- 수록면
- 1 - 6 (6page)
- DOI
- 10.23075/jicas.2021.7.4.001
이용수
초록· 키워드
오류제보하기
Noise Shaping-Successive Approximation Register (NS-SAR) Analog-to-Digital Converters (ADCs) offer high SNDR due to low quantization noise and low comparator noise which has NS-capability. However, to achieve high SNDR, the NS-SAR needs a high bit-quantizer rather than high order NTF limited by stability. A high bit-quantizer offers smaller residue at the end of conversion. This problem is again affected by comparator noise same as SAR, although the comparator noise is shaped by given NTF. This work addresses this issue through pipelined MASH structure which allows high SNDR with a low-quantizer and a low oversampling ratio (OSR), maintaining good stability and wide bandwidth (BW). The dynamic amplifier configured in the loop filter enables high speed and low power. Our proposed ADC operates at 100 MS/s, it consumes 1.9 mW from a 1.2 V supply and achieves 86.69 dB-SNDR and 6.25 MHz-BW, when OSR is 8.
목차
등록된 정보가 없습니다.
참고문헌 (7)
참고문헌 신청
Fredenburg, Jeffrey A. / 2012 / A 90-ms/s 11-mhz-bandwidth 62-db sndr noise-shaping sar adc / IEEE Journal of Solid-State Circuits 47(12):2898~2904
P. Harpe / 2013 / A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10. 1 b ENOB at 2. 2 fJ/conversionstep / IEEE Journal of Solid-State Circuits 47(12):3011~3018
H. Zhuang / 2019 / A Second-Order Noise-Shaping SAR ADC with Passive Integrator and Tri-Level Voting / IEEE Journal of Solid-State Circuits 54(6):1636~1647
Y. Song / 2020 / A 12. 5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC / IEEE Journal of Solid-State Circuits 55(2):312~321
C. -K. Hsu / 2021 / A 77. 1-dB-SNDR 6. 25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping / IEEE Journal of Solid-State Circuits 56(3):739~749
P. Harpe / 2013 / A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10. 1 b ENOB at 2. 2 fJ/conversionstep / IEEE Journal of Solid-State Circuits 47(12):3011~3018
H. Zhuang / 2019 / A Second-Order Noise-Shaping SAR ADC with Passive Integrator and Tri-Level Voting / IEEE Journal of Solid-State Circuits 54(6):1636~1647
Y. Song / 2020 / A 12. 5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC / IEEE Journal of Solid-State Circuits 55(2):312~321
C. -K. Hsu / 2021 / A 77. 1-dB-SNDR 6. 25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping / IEEE Journal of Solid-State Circuits 56(3):739~749
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