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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.4
- 발행연도
- 2024.8
- 수록면
- 332 - 342 (11page)
- DOI
- 10.5573/JSTS.2024.24.4.332
이용수
초록· 키워드
오류제보하기
This paper presents a third-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-time-voltage (V-T-V) converter and mismatch shaping for capacitive digital-to-analog converters (CDACs). To achieve third-order noise shaping, the error feedback (EF) structure and cascade of integrators with feed-forwards (CIFF) structure were cascaded. The amplifier used in EF and CIFF is a V-T-V converter which is insensitive to PVT variation. To implement mismatch shaping, one more CDAC is used to generate residue voltage with data-weighted averaging. The proposed ADC was designed with a 28-nm CMOS process with 1-V power supply. The SPICE simulation results show that the designed ADC has signal-to-noise and distortion ratio (SNDR) of 82.7 dB and power consumption of 435 μW, when operated with a sampling rate of 40-MS/s and oversampling ratio of 10, resulting in a Schreier figure-of-merit (FoM) of 179.4 dB.
목차
Abstract
I. INTRODUCTION
II. PROPOSED NS-SAR ADC
III. CIRCUIT DESCRIPTION
IV. SIMULATION RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (16)
참고문헌 신청
S. Lim, J. Woo Kim, K. Yoon and S. Lee, “A 12-b Asynchronous SAR Type ADC for Bio Signal Detection,” J. Semiconductor Technology and Science, Vol. 13, No. 2, pp. 108-113, Feb. 2013.
L. Kull et al., “A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013.
B. Kim, L. Yan, J. Yoo and H.-J. Yoo, “A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology,” J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32, Jan. 2011.
J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2898-2904, Dec. 2012. doi: 10.1109/JSSC.2012.2217874.
Z. Chen, M. Miyahara and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC," Dig. Tech. Papers 2015 Symp. on VLSI Circuits, pp. C64-C65. doi: 10.1109/VLSIC.2015.7231329.
L. Kull et al., “A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013.
B. Kim, L. Yan, J. Yoo and H.-J. Yoo, “A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology,” J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32, Jan. 2011.
J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2898-2904, Dec. 2012. doi: 10.1109/JSSC.2012.2217874.
Z. Chen, M. Miyahara and A. Matsuzawa, "A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC," Dig. Tech. Papers 2015 Symp. on VLSI Circuits, pp. C64-C65. doi: 10.1109/VLSIC.2015.7231329.
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