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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 IEIE Transactions on Smart Processing & Computing IEIE Transactions on Smart Processing & Computing Vol.10 No.2
- 발행연도
- 2021.4
- 수록면
- 146 - 150 (5page)
- DOI
- 10.5573/IEIESPC.2021.10.2.146
이용수
초록· 키워드
오류제보하기
This paper presents a phase-locked loop (PLL) that reduces reference spurs by using a true random number generator (TRNG). In conventional PLLs, a frequency component of the reference clock appears spurious tones in the voltage-controlled oscillator (VCO) output. In the proposed PLL, the TRNG randomly delays UP/DOWN signals which result in inconsistent timing of charging/discharging at the output of the charge pump (CP). As a result, the CP output disperses the reference spur of the VCO output by making the reference clock frequency component uneven. The proposed PLL was fabricated in a 180-nm CMOS technology. It dissipates 23 mW at 2-GHz with 1.8-V supply and achieves more than 23 dB of additional spur suppression.
목차
Abstract
1. Introduction
2. Circuit Implementation
3. Measurement Results
4. Conclusion
References
참고문헌 (11)
참고문헌 신청
F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, Jan. 1999. Article (CrossRef Link)
D.K. Jeong, et al., “Design of PLL-based clock generation circuits,” IEEE J. Solid-State Circuits, Apr. 1987. Article (CrossRef Link)
B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications,” Proceedings of CICC 97 – Custom Integrated Circuits Conference, CA, USA, pp. 395–402, May. 1997. Article (CrossRef Link)
C. Hung and K.K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. Solid-State Circuits, Aug. 2002. Article (CrossRef Link)
S. Pellerano et al., “A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, Feb. 2004. Article (CrossRef Link)
D.K. Jeong, et al., “Design of PLL-based clock generation circuits,” IEEE J. Solid-State Circuits, Apr. 1987. Article (CrossRef Link)
B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications,” Proceedings of CICC 97 – Custom Integrated Circuits Conference, CA, USA, pp. 395–402, May. 1997. Article (CrossRef Link)
C. Hung and K.K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE J. Solid-State Circuits, Aug. 2002. Article (CrossRef Link)
S. Pellerano et al., “A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, Feb. 2004. Article (CrossRef Link)
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