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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제16권 제5호
- 발행연도
- 2015.1
- 수록면
- 241 - 249 (9page)
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Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.
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참고문헌 (27)
참고문헌 신청
A. C. Kailuke / 2014 / / Proc. of the IEEE 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies : 74 ~ 78
A. Tsitouras / 2011 / / Microelectronics Journal 42 : 1082 ~
B. Bahreyni / 2002 / / Proc. of the the 200245th Midwest Symposium on Circuits and Systems : III-397 ~
C. Jeong / 2013 / / Devices &Systems 7 : 313 ~
C. Weiping / 2011 / / Proc. of the IEEE 2011 Academic International Symposium on Optoelectronics and Microelectronics Technology (AISOMT) : 246 ~ 250
A. Tsitouras / 2011 / / Microelectronics Journal 42 : 1082 ~
B. Bahreyni / 2002 / / Proc. of the the 200245th Midwest Symposium on Circuits and Systems : III-397 ~
C. Jeong / 2013 / / Devices &Systems 7 : 313 ~
C. Weiping / 2011 / / Proc. of the IEEE 2011 Academic International Symposium on Optoelectronics and Microelectronics Technology (AISOMT) : 246 ~ 250
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