지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.3
- 발행연도
- 2020.6
- 수록면
- 288 - 296 (9page)
- DOI
- 10.5573/JSTS.2020.20.3.288
이용수
초록· 키워드
오류제보하기
This paper describes an 8.48-to-11.13 GHz LC-VCO for a 28-nm CMOS transmitter. For the discrete tuning of the LC-VCO, a nearest VCO-curve selection algorithm is proposed, which exhibits additional 1-bit resolution. The proposed algorithm even with the LSB of the capacitor-bank control signal being removed shows the same level of quantization error as the conventional algorithm. The PLL fabricated in a 28-nm CMOS process occupies 0.14 mm². The transmitted PLL clock has a phase noise of −94.21 dBc/Hz at 100-kHz offset and the jitter of 815-fs RMS can be obtained by de-embedding the jitter of the reference clock. The PLL and the driver have power consumption of 3 mW and 23 mW respectively with a 1-V supply at 10.2-GHz LC-VCO frequency.
목차
Abstract
I. INTRODUCTION
II. DISCRETE TUNING ALGORITHM
III. PLL DESIGN BASED ON LC-VCO
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (7)
참고문헌 신청
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T.-H. Lin and W. J. Kaiser, “A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424-431, Mar. 2001.
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W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS self-calibrating frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
A. Pottbacker, U. Langmann, and H. U. Schreiber, “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992.
T.-H. Lin and W. J. Kaiser, “A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 424-431, Mar. 2001.
A. Ravi, G. Banerjee, R. E. Bishop, B. A. Bloechel, L. R. Carley, and K. Soumyanath, “10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 μm digital CMOS process,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 181-184, Jun. 2003.
W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS self-calibrating frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
A. Pottbacker, U. Langmann, and H. U. Schreiber, “A Si bipolar phase and frequency detector IC for clock extraction up to 8 Gb/s,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992.
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