지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.6
- 발행연도
- 2015.12
- 수록면
- 594 - 600 (7page)
이용수
초록· 키워드
오류제보하기
A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from 0° to 360° with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies 0.047 mm². The jitter<SUB>rms</SUB> and jitter<SUB>pk-pk</SUB> of the output clock are 1.91 ps and 18 ps, respectively.
목차
Abstract
I. INTRODUCTION
II. THE PHASE ROTATING PLL DESIGN
III. THE PROPOSED PHASE ROTATING PLL
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (4)
참고문헌 신청
[학술지(정기간행물)] - Rainer Kreienkamp / 2005 / A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator / IEEE J. Solid-State Circuits 40 (3) : 0018 ~ 9200
[학술지(정기간행물)] - Thomas Toifl / 2005 / A 0.94ps-RMSjitter 0.016mm2 2.5GHz multi-phase generator PLL with 360° digitally programmable phase shift for 10Gb/s serial links / IEEE J. Solid-State Circiuts 40 (12) : 2700 ~ 2712
[학술대회논문] - Sungjoon Kim / 2007 / A dual PFD rotating multi-phase PLL for 5Gbps PCI express Gen2 multi-lane serial link receiver in 0.13um CMOS / IEEE Symposium on VLSI Circuits, Papers : 234 ~ 235
[학술대회논문] - Jun-Han Bae / 2012 / A low-power dual- PFD phase rotating PLL with a PFD controller for 5Gb/s serial links / IEEE International Symposium on Circuits and Systems, Papers : 2159 ~ 2162
[학술지(정기간행물)] - Thomas Toifl / 2005 / A 0.94ps-RMSjitter 0.016mm2 2.5GHz multi-phase generator PLL with 360° digitally programmable phase shift for 10Gb/s serial links / IEEE J. Solid-State Circiuts 40 (12) : 2700 ~ 2712
[학술대회논문] - Sungjoon Kim / 2007 / A dual PFD rotating multi-phase PLL for 5Gbps PCI express Gen2 multi-lane serial link receiver in 0.13um CMOS / IEEE Symposium on VLSI Circuits, Papers : 234 ~ 235
[학술대회논문] - Jun-Han Bae / 2012 / A low-power dual- PFD phase rotating PLL with a PFD controller for 5Gb/s serial links / IEEE International Symposium on Circuits and Systems, Papers : 2159 ~ 2162
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