지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.2
- 발행연도
- 2021.4
- 수록면
- 152 - 156 (5page)
- DOI
- 10.5573/JSTS.2021.21.2.152
이용수
초록· 키워드
오류제보하기
A system level power/jitter reduction technique of all-digital phase locked loop (ADPLL) design has been developed. The architecture to memorize the repetitive control signal pattern of digitally-controlled oscillator (DCO) during lock state and to regenerate the pattern, achieve the reduced power consumption compared to conventional mode from 14.4 mW to 9.51 mW in 1.0 V supply at 12.2 GHz and concurrently reduce jitter from 1.86 ps to 1.56 ps. The prototype PLL has been fabricated in 65 nm CMOS process and occupies 0.16 ㎟ chip area.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. MEASUREMENT RESULTS
IV. CONCLUSIONS
REFERENCES
참고문헌 (7)
참고문헌 신청
Nam-Jin Oh and Sang-Gug Lee, “Current reused LC VCOs,” IEEE Microwave and Wireless Compo nents Letters, vol. 15, pp. 736-738, Nov., 2005.
D. Maurath et al., “A Low-Phase Noise 12 GHz Digitally Controlled Oscillator in 65 nm CMOS for a FMCW Radar Frequency Synthesizer,” 12th European Microwave Integrated Circuits Confer ence, Nuremberg, Germany, Oct., 2017, pp. 232-235.
Ching-Yuan Yang et al., “A 0.6 V 10 GHz CMOS VCO Using a Negative-Gm Back-Gate Tuned Technique,” IEEE Microwave and Wireless Components Letters, vol. 21, pp. 163-165, Mar., 2011.
D.-H. Oh, K.-J. Choo and D.-K. Jeong “Phasefrequency detecting time-to-digital converter,” Electronics Letters, vol. 45, pp. 201-202, Feb., 2009.
B. Razavi, “Phase-locking in wireline systems: Present and future,” IEEE Custom Integrated Circuits Conference, Sep., 2008, pp. 615-622.
D. Maurath et al., “A Low-Phase Noise 12 GHz Digitally Controlled Oscillator in 65 nm CMOS for a FMCW Radar Frequency Synthesizer,” 12th European Microwave Integrated Circuits Confer ence, Nuremberg, Germany, Oct., 2017, pp. 232-235.
Ching-Yuan Yang et al., “A 0.6 V 10 GHz CMOS VCO Using a Negative-Gm Back-Gate Tuned Technique,” IEEE Microwave and Wireless Components Letters, vol. 21, pp. 163-165, Mar., 2011.
D.-H. Oh, K.-J. Choo and D.-K. Jeong “Phasefrequency detecting time-to-digital converter,” Electronics Letters, vol. 45, pp. 201-202, Feb., 2009.
B. Razavi, “Phase-locking in wireline systems: Present and future,” IEEE Custom Integrated Circuits Conference, Sep., 2008, pp. 615-622.
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