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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.6
- 발행연도
- 2017.12
- 수록면
- 800 - 805 (6page)
- DOI
- 10.5573/JSTS.2017.17.6.800
이용수
초록· 키워드
오류제보하기
This paper presents a 19.5 ps-LSB vernier-type time-to-digital converter (TDC) to measure the time of flight in a positron emission tomography (PET) imaging system. An 8x8 SiPMs sensor array coupled to LYSO (Lutetium Yttrium Orthosilicate) scintillator crystals are utilized with an anger logic readout circuit to reduce the total number of analog front-end (AFE) channels. The proposed TDC consists of a 5-bit MSB counter and a 6-bit LSB vernier delay line (VDL) TDC that is controlled by an internal delayed-locked loop. A phase-locked loop is integrated for frequency multiplication to increase the time resolution. The prototype chip is fabricated in a 0.18 μm CMOS technology. The measured timing resolutions of the prototype TDC are 400ps with a 333 kHz external input and 5ns using a <SUP>22</SUP>Na point gamma-ray source with an 8x8 SiPMs sensor array and anger logic readout circuit. The prototype TDC consumes 180 mW with a 1.8 V supply voltage while occupying a 1.76 mm² of the active area.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (9)
참고문헌 신청
R.B. Staszewski, J.L. Wallberg, S. Rezeq, Chih- Ming Hung , O.E. Eliezer, S.K. Vemulapalli, C. Fernando, K. Maggio, R. Stazewski, N. Barton, Meng-Chang Lee, P.cruise, M. Entezari, K.Muhammad and D. Leipold, All-digital PLL and transmitter for mobile phones, IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2469- 2482, Dec. 2005.
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, and Francesco Svelto, “A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques” IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 824-834, March 2009.
Jan Nissinen, Ilkka Nissinen, and Juha Kostamovaara, “Integrated Receiver Including Both Receiver Channel and TDC for a Pulsed Time-of-Flight Laser Rangefinder With cm-Level Accuracy” IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp. 1486-1497, May 2009.
H. Menninga, C. Favi, M. W. Fishburn, and E. Charbon, “A multi-channel, 10ps resolution, FPGA-based TDC with 300MS/s throughput for open-source PET applications,” IEEE Nuclear Science Symposium Conference Record, Valencia, 2011, pp. 1515-1522.
A. S. Yousif and J. W. Haslett, “A fine resolution TDC architecture for next generation PET imaging,” IEEE Transactions on Nuclear Science, vol. 54, no. 5, pp. 1574-1582, Oct. 2007.
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