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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.3
- 발행연도
- 2015.6
- 수록면
- 334 - 341 (8page)
이용수
초록· 키워드
오류제보하기
This research outlines the design of a HRTDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a 0.18 μm CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2SVTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. HR-TDC ARCHITECTURE
Ⅲ. SIMULATION AND MEASUREMENT RESULTS
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (9)
참고문헌 신청
[학술대회논문] - A. Elshazly / 2012 / A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC / IEEE Solid-State Circuit Conference Digest of Technical Papers (ISSCC) : 242 ~ 244
[학술대회논문] - Xiaolu Liu / 2011 / A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13μm CMOS / IEEE Annual Conference of The Association of Surgeons of India (ASICON) : 602 ~ 605
[학술지(정기간행물)] - Samarah, A / 2013 / A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC / IEEE J.Solid-State Circuits 48 (8) : 1829 ~ 1841
[학술지(정기간행물)] - M Lee / 2008 / A 9b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue / IEEE J.Solid-State Circuits 43 (4) : 769 ~ 777
[학술대회논문] - Zule Xu / 2013 / A 0.84ps-LSB 2.47mW time-todigital converter using charge pump and SARADC / IEEE Custom Integrated Circuits Conference : 1 ~ 4
[학술대회논문] - Xiaolu Liu / 2011 / A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13μm CMOS / IEEE Annual Conference of The Association of Surgeons of India (ASICON) : 602 ~ 605
[학술지(정기간행물)] - Samarah, A / 2013 / A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC / IEEE J.Solid-State Circuits 48 (8) : 1829 ~ 1841
[학술지(정기간행물)] - M Lee / 2008 / A 9b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue / IEEE J.Solid-State Circuits 43 (4) : 769 ~ 777
[학술대회논문] - Zule Xu / 2013 / A 0.84ps-LSB 2.47mW time-todigital converter using charge pump and SARADC / IEEE Custom Integrated Circuits Conference : 1 ~ 4
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