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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.4
- 발행연도
- 2012.12
- 수록면
- 411 - 417 (7page)
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초록· 키워드
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A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in 0.18 ㎛ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ㎰ with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ㎰.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. TDC ARCHITECTURE
Ⅲ. CIRCUIT DESCRIPTION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (9)
참고문헌 신청
1. [학술지(정기간행물)] - P. Dudek / 2000 / A high-resolution CMOS time-to-digital converter utillizing a Vernier delay line / IEEE J. Solid-State Circuits 35 (2) : 240 ~ 247
2. [학술지(정기간행물)] - M. Lee / 2008 / A 9b, 1.25ps resolution Coarse-Fine Time-to-Digital Converter in 90㎚ CMOS that Amplifies a Time Residue / IEEE J. Solid-State Circuits 43 (4) : 769 ~ 777
3. [학술대회논문] - A. M. Abas / 2004 / Design of sub 10-picoseconds on-chip timemeasurement circuit / Proc. Design AutomationTest Europe Conf 2 : 804 ~ 809
4. [학술지(정기간행물)] - J. P. Janson / 2006 / A CMOS time-to-digital converter with better than 10ps single-shot precision / IEEE J. Solid-State Circuits 41 (6) : 1286 ~ 1296
5. [학술지(정기간행물)] - Jianjun Yu / 2010 / 12-Bit Vernier Ring Time-to-Digital Converter in 0.13㎛ CMOS Technology / IEEE J. Solid-State Circuits 45 (4) : 830 ~ 842
2. [학술지(정기간행물)] - M. Lee / 2008 / A 9b, 1.25ps resolution Coarse-Fine Time-to-Digital Converter in 90㎚ CMOS that Amplifies a Time Residue / IEEE J. Solid-State Circuits 43 (4) : 769 ~ 777
3. [학술대회논문] - A. M. Abas / 2004 / Design of sub 10-picoseconds on-chip timemeasurement circuit / Proc. Design AutomationTest Europe Conf 2 : 804 ~ 809
4. [학술지(정기간행물)] - J. P. Janson / 2006 / A CMOS time-to-digital converter with better than 10ps single-shot precision / IEEE J. Solid-State Circuits 41 (6) : 1286 ~ 1296
5. [학술지(정기간행물)] - Jianjun Yu / 2010 / 12-Bit Vernier Ring Time-to-Digital Converter in 0.13㎛ CMOS Technology / IEEE J. Solid-State Circuits 45 (4) : 830 ~ 842
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UCI(KEPA) : I410-ECN-0101-2014-569-000667797