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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 101 - 104 (4page)
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A group of new memory circuit techniques with the emerging FinFET technology are evaluated in this paper. Three independent-gate FinFET SRAM cells and two multi-threshold-voltage (multi-V<SUB>t</SUB>) work-function engineered SRAM cells are compared for data stability, leakage power consumption, and cell area. The highest read stability is provided by the technique based on dynamically tuning the threshold voltages of the data access transistors during the read and write operations with independent-gate-bias. The read stability is enhanced by up to 92% with the minimum sized dynamic independent-gate-bias FinFET SRAM cells as compared to the minimum sized low-threshold-voltage tied-gate FinFET SRAM cells in a 32nm FinFET technology. Alternatively, the lowest leakage power consumption and the smallest cell area are provided with the work-function engineered multi-Vt FinFET memory cells. The idle mode leakage power and the cell area are reduced by up to 65X and 25.5%, respectively, with the work-function engineered multi-Vt FinFET SRAM cells as compared to a standard low-threshold-voltage (low-Vt) tied-gate FinFET SRAM cell sized for comparable read stability.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. FinFET SRAM CELLS
Ⅲ. SIMULATION RESULTS
Ⅳ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001758397