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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.5
- 발행연도
- 2014.10
- 수록면
- 525 - 536 (12page)
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초록· 키워드
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Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (fT). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.
목차
Abstract
I. INTRODUCTION
II. ANALYTICAL APPROACH FOR MODELING PARASITIC CAPACITANCE AND RESISTANCE
III. LAYOUT OPTIMIZATION CONSIDERING PARASITIC COMPONENTS IN MULTI-FIN FINFETS
IV. CONCLUSIONS
REFERENCES
참고문헌 (23)
참고문헌 신청
1. [기타자료] - / 2013 / The International Technology Roadmap for Semiconductors (ITRS)
2. [학술지(정기간행물)] - 최병길 / 2006 / 이상적인 이중-게이트 벌크 FinFET의 전기적 특성고찰 / 전자공학회논문지 - SD 43 (11) : 1 ~ 7
3. [학술지(정기간행물)] - E. J. Nowak / 2004 / Turning silicon on its edge [double gate MOS/ FinFET technology] / IEEE Circuits and Devices Magazine 20 (1) : 20 ~ 31
4. [학술대회논문] - K. W. Lee / 2012 / Comparative study of analog performance of multiple fin tri-gate FinFETs / International Conference on Electronics, Information and Communication
5. [학술지(정기간행물)] - C. R. Manoj / 2010 / Impact of fringe capacitance on the performance of nanoscale FinFETs / IEEE Electron Device Lett. 31 (1) : 83 ~ 85
2. [학술지(정기간행물)] - 최병길 / 2006 / 이상적인 이중-게이트 벌크 FinFET의 전기적 특성고찰 / 전자공학회논문지 - SD 43 (11) : 1 ~ 7
3. [학술지(정기간행물)] - E. J. Nowak / 2004 / Turning silicon on its edge [double gate MOS/ FinFET technology] / IEEE Circuits and Devices Magazine 20 (1) : 20 ~ 31
4. [학술대회논문] - K. W. Lee / 2012 / Comparative study of analog performance of multiple fin tri-gate FinFETs / International Conference on Electronics, Information and Communication
5. [학술지(정기간행물)] - C. R. Manoj / 2010 / Impact of fringe capacitance on the performance of nanoscale FinFETs / IEEE Electron Device Lett. 31 (1) : 83 ~ 85
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UCI(KEPA) : I410-ECN-0101-2015-560-002808575