지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 333 - 336 (4page)
이용수
초록· 키워드
오류제보하기
Data stability is a major concern in today’s high performance memory circuits with deeply scaled transistors and power supply voltages. Multi-threshold-voltage (multi-Vt) ninetransistor (9T) Static Random Access Memory (SRAM) cells with enhanced data stability and superior overall electrical quality characteristics are presented in this paper. 9T SRAM cells eliminate the data disturbance by isolating the bitlines from data storage nodes during read operations. The design tradeoffs of 9T multi-Vt SRAM cells are explored with a TSMC 65nm CMOS technology that provides a rich set of device threshold voltage options. A triple-threshold-voltage 9T memory cell offers up to 9.7X higher overall electrical quality as compared to a previously published single-threshold-voltage 9T SRAM cell.
목차
Abstract
I. INTRODUCTION
II. TRANSISTOR THRESHOLD VOLTAGE OPTIONS
III. CHARACTERIZATION OF 9T SRAM CIRCUITS
IV. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001475062