지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.9 No.1
- 발행연도
- 2009.3
- 수록면
- 29 - 36 (8page)
이용수
초록· 키워드
오류제보하기
Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. BACKGROUND
Ⅲ. CURRENT WAVEFORM ESTIMATION USING CELL LIBRARY INFORMATION
Ⅳ. CLOCK SCHEDULING ALGORITHM FOR POWER SUPPLY NOISE REDUCTION
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS AND FUTURE WORK
REFERENCES
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