지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 537 - 540 (4page)
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초록· 키워드
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This paper overviews dual-supply design for low-power mobile systems in deep sub-micron technology. Various dual-supply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dual-supply design applied to a clock network was more efficient than that applied to data-path logics. For example, the dual-supply clock network with clock-gating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clock-gating level converter can enable a system to exploit pulse-based flip-flops without pulse generators, resulting in more power reduction.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DATA PATH-INTENSIVE APPROACHES
Ⅲ. CLOCK NETWORK-INTENSIVE APPROACHES
Ⅳ. CONCLUSION
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UCI(KEPA) : I410-ECN-0101-2014-569-000730364