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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 669 - 670 (2page)
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이 논문의 연구 히스토리 (4)
2008
A High-Level Power Estimation Methodology for Low Power Design
Chi-Ho Lin
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2008.07
학술대회자료
A New Efficient High-Level Synthesis Methodology for Lower Power
Chi-Ho Lin
ICEIC : International Conference on Electronics, Informations and Communications
2008.06
학술대회자료
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초록· 키워드
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In this paper, we present a new clock skew scheduling methodology for high-level power optimization to optimize the power consumption in the synthesized data path.
In this paper, The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the in ... 전체 초록 보기
In this paper, The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the in ... 전체 초록 보기
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UCI(KEPA) : I410-ECN-0101-2012-569-004021404