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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.1
- 발행연도
- 2013.2
- 수록면
- 71 - 78 (8page)
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초록· 키워드
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In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.
목차
Abstract
I. INTRODUCTION
II. RELATED WORK
III. ON-CHIP TEST CLOCK CONTROL SCHEME
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (25)
참고문헌 신청
1. [학술지(정기간행물)] - C. H. Tung / 2003 / Process-Structure-Property Relationship and its Impact on Microelectronics Device Reliability and Failure Mechanism / Journal of Semiconductor Technology and Science (JSTS) 3 (3) : 107 ~ 113
2. [학술지(정기간행물)] - W. Wang / 2007 / Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology / IEEE Trans. on Device and Material Reliability 7 (4) : 509 ~ 517
3. [학술대회논문] - T. W. Chen / 2008 / Gate-Oxide Early Failure Prediction / Proc. IEEE VLSI Test Symp. : 111 ~ 118
4. [학술대회논문] - M. Noda / 2010 / On Estimation of NBTI-Induced Delay Degradation / IEEE European Test Symp. : 107 ~ 111
5. [학술대회논문] - O. Khan / 2009 / A Self-Adaptive System Architecture to Address Transistor Aging / Proc. Design Automation and Test in Europe : 81 ~ 86
2. [학술지(정기간행물)] - W. Wang / 2007 / Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology / IEEE Trans. on Device and Material Reliability 7 (4) : 509 ~ 517
3. [학술대회논문] - T. W. Chen / 2008 / Gate-Oxide Early Failure Prediction / Proc. IEEE VLSI Test Symp. : 111 ~ 118
4. [학술대회논문] - M. Noda / 2010 / On Estimation of NBTI-Induced Delay Degradation / IEEE European Test Symp. : 107 ~ 111
5. [학술대회논문] - O. Khan / 2009 / A Self-Adaptive System Architecture to Address Transistor Aging / Proc. Design Automation and Test in Europe : 81 ~ 86
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