지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.4
- 발행연도
- 2024.8
- 수록면
- 355 - 364 (10page)
- DOI
- 10.5573/JSTS.2024.24.4.355
이용수
초록· 키워드
오류제보하기
This paper presents a 2-GS/s 6-bit single-channel speculative loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with comparator offset calibration. The proposed loop-unrolled SAR ADC speeds up its conversion speed by selecting one of the pre-determined capacitive digital-to-analog converters (CDACs) speculatively. A foreground comparator offset calibration for the speculative loop-unrolled SAR ADC is introduced to improve the ADC performance by reducing the input parasitic capacitance and minimizing the logic fan-out in comparator internal clock path. The CDAC switching method that minimizes the variation of the output common-mode (CM) voltage is applied to be compatible with the proposed foreground comparator offset calibration. In addition, the modified double-tail comparator structure is adopted for reducing the kickback noise without the speed overhead. The proposed SAR ADC achieves a 2-GS/s sampling rate with only a single-channel without a time-interleaving technique. The ADC is fabricated in 28-nm CMOS and has a 33.1-dB SNDR at a low input frequency and a 29.9-dB SNDR at the Nyquist frequency with a 6.2- mW power consumption from 1.2-V supply voltage.
목차
Abstract
I. INTRODUCTION
II. SPECULATIVE LOOP-UNROLLED SAR ADC
III. COMPARATOR OFFSET CALIBRATION FOR SPECULATIVE LOOP-UNROLLED SAR ADC
IV. DESIGN IMPLEMENTATIONS
V. MEASUREMENT RESULTS
IV. CONCLUSION
REFERENCES
참고문헌 (11)
참고문헌 신청
S. Kiran, S. Cai, Y. Luo, S. Hoyos and S. Palermo, "A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS," in IEEE J. of Solid-State Circuits, vol. 54, no. 3, pp. 659-671, Mar. 2019.
Y. Frans, J. Shin, P. Upadhyaya, J. Im, V. Kireev, M. Elzeftawi, H. Hedayati, T. Pham, S. Asuncion, C. Borrelli, G. Zhang, H. Zhang, K. Chang, "A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET," in IEEE J. of Solid-State Circuits, vol. 52, no. 4, pp. 1101-1110, Apr. 2017.
C. -H. Chan, Y. Zhu, W. -H. Zhang, S. -P. U and R. P. Martins, "A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration," in IEEE J. of Solid-State Circuits, vol. 53, no. 3, pp. 850-860, Mar. 2018.
B. -R. -S. Sung, D. -S. Jo, I. -H. Jang, D. -S. Lee, Y. -S. You, Y. -H. Lee, H. -J. Park, S. -T. Ryu, "26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS," Dig. Tech. Pap. – IEEE Int. Solid-State Circuits Conf (ISSCC), pp. 1-3, Feb. 2015.
L. Chen, K. Ragab, X. Tang, J. Song, A. Sanyal and N. Sun, "A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS," in IEEE Trans Circuits and Syst. II, vol. 64, no. 3, pp. 244-248, Mar. 2017.
Y. Frans, J. Shin, P. Upadhyaya, J. Im, V. Kireev, M. Elzeftawi, H. Hedayati, T. Pham, S. Asuncion, C. Borrelli, G. Zhang, H. Zhang, K. Chang, "A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET," in IEEE J. of Solid-State Circuits, vol. 52, no. 4, pp. 1101-1110, Apr. 2017.
C. -H. Chan, Y. Zhu, W. -H. Zhang, S. -P. U and R. P. Martins, "A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration," in IEEE J. of Solid-State Circuits, vol. 53, no. 3, pp. 850-860, Mar. 2018.
B. -R. -S. Sung, D. -S. Jo, I. -H. Jang, D. -S. Lee, Y. -S. You, Y. -H. Lee, H. -J. Park, S. -T. Ryu, "26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS," Dig. Tech. Pap. – IEEE Int. Solid-State Circuits Conf (ISSCC), pp. 1-3, Feb. 2015.
L. Chen, K. Ragab, X. Tang, J. Song, A. Sanyal and N. Sun, "A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS," in IEEE Trans Circuits and Syst. II, vol. 64, no. 3, pp. 244-248, Mar. 2017.
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
A 6 bits 10 MS/s Asynchronous Loop-Unrolled SAR ADC
대한전자공학회 학술대회
2024 .06
-
An 80 dB Second-order Noise Shaping SAR ADC using Differential Integral Capacitors and Comparator with Voltage Gain Calibration
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .08
-
오프셋 보정기술을 이용한 8비트 200MS/s 축차 근사형 아날로그-디지털 변환기 설계
대한전자공학회 학술대회
2024 .11
-
A 10-bit 263 kS/s SAR ADC in 180 nm CMOS with Input Offset Compensation of Comparator
대한전자공학회 학술대회
2017 .01
-
에너지 소모량과 면적을 개선한 하이브리드 SAR ADC
한국전자파학회논문지
2021 .09
-
Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2021 .10
-
저전력 37uW 10-bit 모노토닉 축차비교형 아날로그 디지털 변환기
대한전자공학회 학술대회
2023 .06
-
A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .12
-
Histogram기반 자가보정 SAR 아날로그-디지털 컨버터
대한전자공학회 학술대회
2020 .11
-
Foreground Digital Calibration for Split-Capacitor DAC in SAR ADC
대한전자공학회 학술대회
2022 .11
-
소자 부정합에 덜 민감한 12비트 60MS/s 0.18um CMOS Flash-SAR ADC
전자공학회논문지
2016 .07
-
A 12-bit 40 MS/s SAR ADC with Digital Foreground Self-calibration for Capacitor Mismatches
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2020 .02
-
보조 Coarse ADC를 사용한 고속 SAR-ADC
대한전자공학회 학술대회
2018 .06
-
Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System
IEIE Transactions on Smart Processing & Computing
2015 .06
-
A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2015 .10
-
비이진 기법을 사용한 9.5-ENOB 10비트 409MS/s 파이프라인 축차 근사형 아날로그-디지털 변환기 설계
대한전자공학회 학술대회
2024 .11
-
8-bit 2-step Flash-SAR ADC
대한전자공학회 학술대회
2024 .06
-
캐패시터 기반의 고정밀 옵셋조절이 가능한 SAR ADC
대한전자공학회 학술대회
2018 .06
-
Reference Driver를 사용한 10비트 10MS/s 축차근사형 아날로그-디지털 변환기
한국정보통신학회논문지
2016 .12
-
저전력, 중간 해상도 잡음 변조 기법 아날로그 디지털 변환기
대한전자공학회 학술대회
2019 .11
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-151-24-02-090271162