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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제22권 제5호
- 발행연도
- 2021.10
- 수록면
- 598 - 602 (5page)
- DOI
- https://doi.org/10.1007/s42341-021-00355-8
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초록· 키워드
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Depletion load type of logic circuits using only n-type amorphous Si?In?Zn?O (a-SIZO) as channel material have been fabricated and used to analyze the threshold voltage (V TH ) with respect to the a-SIZO channel thickness. The channel thickness was controlled by varying the deposition time. As channel thickness increased from 30 to 45 nm, V TH , on current, field effect mobility changed from 0.86 to 0.39 V, 9.30 × 10 ?5 A?1.10 × 10 ?4 A, and 4.36?6.98 cm 2 /V s, respectively. Inverter behavior has been extracted by voltage transfer curve by applying the V DD from 1 to 5 V. The voltage gain of inverter was obtained as 0.90 at V DD = 5 V. It was also confirmed that n-type based NAND thin film circuit works exactly same as the truth table. This simple fabrication method of amorphous oxide semiconductor thin film logic circuit could provide the possibility that we can make the inverter despite the small diff erence in V TH .
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