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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 1,445 - 1,448 (4page)
이용수
이 논문의 연구 히스토리 (4)
2008
A High-Level Power Estimation Methodology for Low Power Design
Chi-Ho Lin
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2008.07
학술대회자료
A New Efficient High-Level Synthesis Methodology for Lower Power
Chi-Ho Lin
ICEIC : International Conference on Electronics, Informations and Communications
2008.06
학술대회자료
- 이 논문의 후속연구가 궁금하신가요?
- 연관 학술논문 또는 학술발표를 통해 보다 발전된 연구결과를 확인하실 수 있습니다.
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초록· 키워드
오류제보하기
This work is a contribution to high-level synthesis for low power systems. In this paper, we present an efficient algorithm on performing estimation with an aim of reducing the power consumption in the synthesized data path.
In this paper, CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, The power estimation methods on enable power management and module selection are performed, so as to reduce the power consumption in low power design.
The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.
In this paper, CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, The power estimation methods on enable power management and module selection are performed, so as to reduce the power consumption in low power design.
The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.
목차
Abstract
1. Introduction
2. The new synthesis algorithm for low power design
3. The High-Level Power Estimation Methodology
4. Experimental Results
5. Conclusion
Reference
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UCI(KEPA) : I410-ECN-0101-2013-569-001142131