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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.2
- 발행연도
- 2012.6
- 수록면
- 139 - 149 (11page)
이용수
초록· 키워드
오류제보하기
A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. 3D CLOCK TREE AND ON-PACKAGE VARIATION
Ⅲ. POST SILICON 3D CLOCK SKEW MANAGEMENT WITH BODY BIASING TECHNIQUE
Ⅳ. PARAMETRIC YIELD IMPROVEMENT OF 3D CLOCK SKEW
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-002636689