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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.10 No.2
- 발행연도
- 2010.6
- 수록면
- 118 - 129 (12page)
이용수
초록· 키워드
오류제보하기
A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (σVth) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-㎚ CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to 6σ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. REDUCING MISMATCH OF CELL-MARGIN CHARACTERISTICS
Ⅲ. DISTURB-FREE BIASING SCHEME
Ⅳ. EVALUATION RESULTS
Ⅴ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (15)
참고문헌 신청
1. [학술대회논문] - T. Suzuki / 2007 / A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Bising Scheme / IEEE Custom Integrated Circuits Conference : 35 ~ 38
2. [기타자료] - Y. Komatsu / 2005 / Substrate-Noise and random-Variations Reduction with Self-Adjusted Forward Body Bias / IEEE Custom Integrated Circuits Conference : 2005 ~
3. [학술대회논문] - G. Tsutui / 2008 / Reduction of Vth variation by work function optimization for 45-nm node SRAM cell / Symp.VLSI Technology., Digest of Technical Papers : 158 ~ 159
4. [학술대회논문] - R. Tsuchiya / 2009 / Low Voltage (Vdd-0.6V) SRAM Operation Achived by Reduced Threshold Voltage Variability in SOTB (Silicon on Thin BOX) / Symp.VLSI Technology., Digest of Technical Papers : 150 ~ 151
5. [학술대회논문] - K. Zhang / 2005 / A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply / IEEE International Solid-State Circuits Conference, Digest of Technical Papers : 474 ~ 475
2. [기타자료] - Y. Komatsu / 2005 / Substrate-Noise and random-Variations Reduction with Self-Adjusted Forward Body Bias / IEEE Custom Integrated Circuits Conference : 2005 ~
3. [학술대회논문] - G. Tsutui / 2008 / Reduction of Vth variation by work function optimization for 45-nm node SRAM cell / Symp.VLSI Technology., Digest of Technical Papers : 158 ~ 159
4. [학술대회논문] - R. Tsuchiya / 2009 / Low Voltage (Vdd-0.6V) SRAM Operation Achived by Reduced Threshold Voltage Variability in SOTB (Silicon on Thin BOX) / Symp.VLSI Technology., Digest of Technical Papers : 150 ~ 151
5. [학술대회논문] - K. Zhang / 2005 / A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply / IEEE International Solid-State Circuits Conference, Digest of Technical Papers : 474 ~ 475
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