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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.11
- 수록면
- 158 - 161 (4page)
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SRAM data stability and leakage currents are major concerns in nanometer CMOS technologies. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. A seven-transistor (7T) SRAM cell provides enhanced data stability by isolating the bitlines from data storage nodes during a read operation. The design tradeoffs in a 7T SRAM cell are explored in this paper with a UMC 80nm multi-threshold-voltage CMOS technology that provides a rich set of device options. An electrical performance metric is proposed to evaluate and compare the memory circuits. The multi-threshold-voltage SRAM circuits offering the highest data stability, widest write margin, smallest read and write power consumption, and lowest leakage currents are identified.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. 7T TRIPLE-VtSRAM CIRCUITS
Ⅲ. SIZING AND LAYOUT OF 7T SRAM CELLS
Ⅳ. CHARACTERIZATION OF 7T SRAM CIRCUITS
Ⅴ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001489184