지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.3
- 발행연도
- 2024.6
- 수록면
- 208 - 217 (10page)
- DOI
- 10.5573/JSTS.2024.24.3.208
이용수
초록· 키워드
오류제보하기
This paper proposes a pulse amplitude modulation-4 (PAM-4) baud-rate clock and data recovery (CDR) circuit with improved jitter tolerance using a shared sampler method. In the proposed design technique, each sampler output is used simultaneously for data decoding and phase detection. Since all samplers are used for phase detection, it has improved jitter tolerance based on high transition density. In this design, the transition density is 0.375. In addition, only four samplers are used per UI, which enables an energy efficient CDR design. Furthermore, the proposed phase detector (PD) minimizes CDR lock point fluctuations by employing pattern-based PD. The receiver with proposed CDR is implemented in a 65-nm CMOS process and has a target of 25 Gb/s data rate. The power consumption of the receiver is 19.6 mW with -7.1 dB channel loss. The energy efficiency of the receiver is 0.784 pJ/bit.
목차
Abstract
I. INTRODUCTION
II. BACKGROUND
III. ARCHITECTURE
IV. SHARED SAMPLER METHOD
V. SIMULATION RESULTS
VI. CONCLUSIONS
REFERENCES
참고문헌 (11)
참고문헌 신청
L. Tang, W. Gai, L. Shi and X. Xiang, "A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery," Symposium on Circuits and Systems, 2017. ISCAS2017. IEEE International, 28-31, pp. 1-4, May, 2017.
M. Verbeke, G. Torfs and P. Rombouts, "The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs," Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 68, No. 1, pp. 469-482, Jan., 2021.
D. -H. Kwon, M. Kim, S. -G. Kim and W. -Y. Choi, "A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector," Circuits and Systems II: Express Briefs, IEEE Transactions on, Vol. 66, No. 3, pp. 362-366, Mar., 2019.
W. Jung, K. Lee, K. Park, H. Ju, J. Lee and D. -K. Jeong, "A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS," Solid-State Circuits, IEEE Journal of, Vol. 58, No. 5, pp. 1414-1424, May, 2023.
H. Ju, K. Lee, K. Park, W. Jung and D. -K. Jeong, "Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 10, pp. 3014-3024, Oct., 2022.
M. Verbeke, G. Torfs and P. Rombouts, "The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs," Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 68, No. 1, pp. 469-482, Jan., 2021.
D. -H. Kwon, M. Kim, S. -G. Kim and W. -Y. Choi, "A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector," Circuits and Systems II: Express Briefs, IEEE Transactions on, Vol. 66, No. 3, pp. 362-366, Mar., 2019.
W. Jung, K. Lee, K. Park, H. Ju, J. Lee and D. -K. Jeong, "A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS," Solid-State Circuits, IEEE Journal of, Vol. 58, No. 5, pp. 1414-1424, May, 2023.
H. Ju, K. Lee, K. Park, W. Jung and D. -K. Jeong, "Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 10, pp. 3014-3024, Oct., 2022.
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