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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.3 No.4
- 발행연도
- 2017.10
- 수록면
- 1 - 7 (7page)
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초록· 키워드
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A DLL-based reference-less CDR for clock-embedded signaling in 65nm CMOS is presented. The proposed receiver operates in mixed mode and the supply voltage is 1.0 V. To save the channel for forwarded clock and eliminate the external reference, clock-embedded signaling scheme is used in this proposal. DLL-based architecture is adopted to save the power consumption. To accomplish a 10Gb/s data rate, inter-symbol-interference (ISI) jitter reduction technique is presented. ISI jitter reduction reduces the bit-error rate (BER) of the receiver by enlarging the sampling margin. To save the power consumption, new deskew method which is done by sub-DLL is presented to use D-flip flops instead of sense-amps. The sub-DLL also gives tolerance to PVT variations to the receiver. The post-layout simulation results, which were done with the Samsung 65nm process model, verify the operation of the proposed schemes.
목차
등록된 정보가 없습니다.
참고문헌 (8)
참고문헌 신청
Sui Huang / 2015 / An 8. 2Gb/s-to-10. 3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0. 18 μm CMOS / Solid-State Circuits, IEEE Journal 50(9):2048~2060
Dong Hoon Baek / 2014 / 2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface / Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International :48~49
Junyoung Song / 2013 / A 1. 62 Gb/s–2. 7 Gb/s Referenceless Transceiver for DisplayPort v1. 1a With Weighted Phase and Frequency Detection / Circuits and Systems I: Regular Papers, IEEE Transactions on 60(2):268~278
G. Shu / 2014 / A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS / IEEE ISSCC Dig. Tech. Papers :150~151
G. Shu / 2014 / A reference-less clock and data recovery circuit using phase-rotating phase-locked loop / IEEE J. Solid-State Circuits 49(4):1036~1047
Dong Hoon Baek / 2014 / 2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface / Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International :48~49
Junyoung Song / 2013 / A 1. 62 Gb/s–2. 7 Gb/s Referenceless Transceiver for DisplayPort v1. 1a With Weighted Phase and Frequency Detection / Circuits and Systems I: Regular Papers, IEEE Transactions on 60(2):268~278
G. Shu / 2014 / A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS / IEEE ISSCC Dig. Tech. Papers :150~151
G. Shu / 2014 / A reference-less clock and data recovery circuit using phase-rotating phase-locked loop / IEEE J. Solid-State Circuits 49(4):1036~1047
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