지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.3
- 발행연도
- 2021.6
- 수록면
- 199 - 205 (7page)
- DOI
- 10.5573/JSTS.2021.21.3.199
이용수
초록· 키워드
오류제보하기
A phase interpolator (PI) based all-digital clock and data recovery (CDR) system has been fabricated in 65 nm CMOS process. The segmented switching units control the slew rate of input clock signal in the PI and the linearity of PI control code and output phase shift steps is improved by 0.4 LSB for standard deviation of differential nonlinearity (DNL). The measurement results show that our CDR locks successfully for 6 Gbit/s non-return to zero (NRZ) high-speed signal with 2<SUP>31-1</SUP> pseudo-random bit sequence (PRBS) pattern. The input NRZ input signal has 2.05 ps of root-mean square (RMS) jitter and 1 V<SUB>dpp</SUB> of swing. When the loop is locked, the output clock signal shows 12.2 ps of peak-to-peak jitter and 1.826 ps of RMS jitter, which is divide 16 speed of the full rate. The measured phase noise of the recovered clock is -114.72 dBc/Hz at 1 MHz offset. The designed built-in pattern checker in receiver exhibits 10<SUP>-12</SUP> of bit error rate (BER) at the center of data eye. The lock time of the loop measured via 7-bit monitoring digital-to-analog converter (DAC) is 54.5 ns. The prototype CDR occupies 0.073 mm² chip area and consumes 17.4 mW from 1.0 V power supply.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. CIRCUIT DESCRIPTION
IV. MEASUREMENT RESULTS
V. CONCLUSION
REFERENCES
참고문헌 (18)
참고문헌 신청
R. Shivnaraine et al., “An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset",” IEEE Trans. on Circuits and Systems-I, vol. 61, pp.2129-2138, July., 2014.
A. Kiaei et al., “A 10 Gb/s NRZ receiver with feedforward equalizer and glitch-free phasefrequency detector,” Proceeding of European Solid-State Circuits Conference, pp.372-375, Sep., 2009.
J. Jin et al., “A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector,” IEEE J. Solid-State Circuits, vol. 53, pp.2994-3003, Oct., 2018.
A. Elshazly et al., “A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration,” IEEE J. Solid-State Circuits, Vol. 46, No. 12, pp. 2759-2771.
G. Shu et al., “A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous rate digital CDR with automatic frequency acquisition in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., San Francisco, CA, Feb., 2014, pp.150-151.
A. Kiaei et al., “A 10 Gb/s NRZ receiver with feedforward equalizer and glitch-free phasefrequency detector,” Proceeding of European Solid-State Circuits Conference, pp.372-375, Sep., 2009.
J. Jin et al., “A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector,” IEEE J. Solid-State Circuits, vol. 53, pp.2994-3003, Oct., 2018.
A. Elshazly et al., “A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration,” IEEE J. Solid-State Circuits, Vol. 46, No. 12, pp. 2759-2771.
G. Shu et al., “A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous rate digital CDR with automatic frequency acquisition in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., San Francisco, CA, Feb., 2014, pp.150-151.
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