지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.3
- 발행연도
- 2015.6
- 수록면
- 404 - 416 (13page)
이용수
초록· 키워드
오류제보하기
Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE
Ⅲ. CIRCUIT IMPLEMENTATION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (24)
참고문헌 신청
[학술지(정기간행물)] - Pavan Kumar Hanumolu / 2008 / A Wide-Tracking Range Clock and Data Recovery Circuit / IEEE J. Solid-State Circuits 43 (2) : 268 ~ 278
[학술지(정기간행물)] - Arnoud P. van der Wel / 2012 / A 1.2–6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 m CMOS / IEEE J. Solid-State Circuits 47 (7) : 1768 ~ 1775
[학술대회논문] - Fan-Ta Chen / 2011 / A 10 to 11.5GHz Rotational Phase and Frequency Detector for Clock Recovery Circuit / Circuits and Systems (ISCAS), 2011 IEEE International Symposium on : 185 ~ 188
[학술지(정기간행물)] - Jri Lee / 2009 / A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition / IEEE J. Solid- State Circuits 44 (12) : 3590 ~ 3602
[학술지(정기간행물)] - Namik Kocaman / 2013 / An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition / IEEE J. Solid-State Circuits 48 (8) : 1875 ~ 1884
[학술지(정기간행물)] - Arnoud P. van der Wel / 2012 / A 1.2–6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 m CMOS / IEEE J. Solid-State Circuits 47 (7) : 1768 ~ 1775
[학술대회논문] - Fan-Ta Chen / 2011 / A 10 to 11.5GHz Rotational Phase and Frequency Detector for Clock Recovery Circuit / Circuits and Systems (ISCAS), 2011 IEEE International Symposium on : 185 ~ 188
[학술지(정기간행물)] - Jri Lee / 2009 / A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition / IEEE J. Solid- State Circuits 44 (12) : 3590 ~ 3602
[학술지(정기간행물)] - Namik Kocaman / 2013 / An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition / IEEE J. Solid-State Circuits 48 (8) : 1875 ~ 1884
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