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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.4 No.4
- 발행연도
- 2018.10
- 수록면
- 21 - 31 (11page)
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초록· 키워드
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This paper presents a design of 5-channel receiver for ocean acoustic measurement in a very noisy environment. When measuring the distance in the ocean with the sonar signal, the input signal level to the receiver is drastically changed depending on the distance between the transmitter and objects. Thus, the receiver with high sensitivity and wide dynamic range is proposed in this work. In order to minimize the Input-Referred (IR) noise for high sensitivity of the receiver, low noise pre-amplifier is proposed and implemented achieving the noise of 29.6 nV/√Hz at 50 kHz. In addition, Sigma-Delta Analog-to-Digital Converter (SD ADC) with variable sampling rates is proposed by using clock splitting technique in the Sigma-Delta Modulator (SDM) core. Also, the decimation factor of the digital filter placed after the SDM in the SD ADC can be controlled to reduce the power consumption. Thanks to these techniques in the SD ADC, we can implement the reconfigurable sampling rates from 1.5 MS/s to 12.5 MS/s with low power consumption. In order to overcome the limitation of the number of pins for multi-channel application, Parallel-to-Serial (P2S) interface is proposed and designed in the receiver. The 5-channel receiver in this paper is implemented in 0.18μm CMOS process and die area is 14.44 mm2. The total power consumption of this chip is 46.8 mW under the supply voltage of 2.4 V. The measured sensitivity and dynamic range are -100 dBV and 100 dB, respectively. The measured SNDR at the output of the SD ADC is 82.02 dB when the input signal frequency and sampling frequency are 7 kHz and 6.25 Msps, respectively. The maximum phase error between 5 channels is measured to be ± 0.8 °.
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참고문헌 (13)
참고문헌 신청
Susie Kim / 2018 / A 2-MHz BW 82-dB DR Continuous-Time Delta–Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation / IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26(10):1999~2006
Weng, C.-H. / 2017 / A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer / IEEE Transactions on Circuits and Systems I: Regular Papers 64:1085~1093
Kim, T.-W. / 2016 / A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator / IEEE Journal of Solid-State Circuits 51:1840~1850
Chu, C. / 2013 / Analysis and design of high speed/high linearity continuous time delta-sigma modulator / 2013 IEEE International Symposium on Circuits and Systems :1268~1271
Caldwell, T. / 2017 / High-Speed Oversampled Continuous-Time Analog-to-Digital Converters / 2017 IEEE 60th International Midwest Symposium on Circuits and Systems :1001~1004
Weng, C.-H. / 2017 / A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer / IEEE Transactions on Circuits and Systems I: Regular Papers 64:1085~1093
Kim, T.-W. / 2016 / A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator / IEEE Journal of Solid-State Circuits 51:1840~1850
Chu, C. / 2013 / Analysis and design of high speed/high linearity continuous time delta-sigma modulator / 2013 IEEE International Symposium on Circuits and Systems :1268~1271
Caldwell, T. / 2017 / High-Speed Oversampled Continuous-Time Analog-to-Digital Converters / 2017 IEEE 60th International Midwest Symposium on Circuits and Systems :1001~1004
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