지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.3
- 발행연도
- 2016.6
- 수록면
- 300 - 311 (12page)
이용수
초록· 키워드
오류제보하기
The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.
목차
Abstract
I. INTRODUCTION
II. ADC-BASED RECEIVER ARCHITECTURE
III. FRONT-END ADC
IV. DIGITAL EQUALIZER
V. SYSTEM-LEVEL OPTIMIZATION
VI. CONCLUSION
REFERENCES
참고문헌 (25)
참고문헌 신청
[학술대회논문] - Harwood, M. / 2007 / A 12.5Gb/s SerDes in 65nm CMOS using a baud- rate ADC with digital receiver equalization and clock recovery / IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers : 436 ~ 437
[학술대회논문] - Cao, J. / 2009 / A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s serial links over backplane and multimode fiber / IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers : 370 ~ 371
[학술대회논문] - Chen, E.-H. / 2011 / 10Gb/s serial I/O receiver based on variable reference ADC / IEEE Symp. VLSI Circuits Dig. Tech. Papers : 288 ~ 289
[학술지(정기간행물)] - Kim, J. / 2011 / Equalizer design and performance trade-offs in ADC-based serial links / IEEE Trans. Circuits Syst. I 58 (8) : 2096 ~ 2107
[학술지(정기간행물)] - Chen, E. -H. / 2012 / Power optimized ADC-based serial link receiver / IEEE J. Solid-State Circuits 47 (4) : 938 ~ 951
[학술대회논문] - Cao, J. / 2009 / A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s serial links over backplane and multimode fiber / IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers : 370 ~ 371
[학술대회논문] - Chen, E.-H. / 2011 / 10Gb/s serial I/O receiver based on variable reference ADC / IEEE Symp. VLSI Circuits Dig. Tech. Papers : 288 ~ 289
[학술지(정기간행물)] - Kim, J. / 2011 / Equalizer design and performance trade-offs in ADC-based serial links / IEEE Trans. Circuits Syst. I 58 (8) : 2096 ~ 2107
[학술지(정기간행물)] - Chen, E. -H. / 2012 / Power optimized ADC-based serial link receiver / IEEE J. Solid-State Circuits 47 (4) : 938 ~ 951
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UCI(KEPA) : I410-ECN-0101-2017-569-000775418