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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2024.11
- 수록면
- 1,275 - 1,280 (6page)
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초록· 키워드
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Sigma-Delta Analog-to-Digital Converters (SD-ADCs) are widely regarded as a pivotal solution for high-precision sensor applications due to their exceptional noise-shaping capabilities and high-resolution performance. In this work, we present the design and implementation of a high-efficiency Sigma-Delta ADC optimized for low-power sensor applications. The structure has feedback loop mechanism with self-biasing technique in integrator block. The proposed architecture operates with an input supply voltage of 1.2V and a sampling frequency of 2 MHz, effectively capturing input signals with a frequency of 1.7 kHz. This modulator structure achieves a Signal-to-Noise Ratio (SNR) of 95 dB, corresponding to an Effective Number of Bits (ENOB) of 15.4. This performance is attained with a total power consumption of 1.4 mW, demonstrating the modulator's suitability for portable and energy-constrained sensor systems. The design implemented by using the 0.13um CMOS technology.
목차
Abstract
I. Introduction
II. Structure Implementation
Ⅲ. Measurement Result
Ⅳ. Conclusion
Reference
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