지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.18 No.4
- 발행연도
- 2018.8
- 수록면
- 525 - 535 (11page)
- DOI
- 10.5573/JSTS.2018.18.4.525
이용수
초록· 키워드
오류제보하기
A wide-gain-range Intermediate Frequency (IF) integrated circuit is designed and implemented for a superheterodyne receiver in standard 0.18 μm CMOS technology. It consists mainly of a programmable attenuator, a Variable Gain Amplifier (VGA), a downconverting mixer and a fixed gain amplifier. The π-type-network attenuator is chosen over a T-type network one in order for a compact layout. The common-gate-input VGA is used for a high operation frequency, a small phase shift and a wide gain range. The common-gate Gilbert-type mixer with a dynamic current injection technique and a capacitive cross-coupling technique is employed for proper gain, low noise and high linearity. Furthermore, a Phase-Locked Loop (PLL) is also integrated monolithically so as to generate the desired local clock signal for the mixer. Measurement results show that, from an area of 2.16 mm×1.46 mm and power consumption of 234 mW, the IF chip is able to operate properly with a gain range of 5 dB ~ 57 dB, output power of above 0dBm, and so on. In addition, the on-chip local clock with an operation frequency of 660 MHz and a phase noise of -119.34 dBc @1 MHz is achieved.
목차
Abstract
I. INTRODUCTION
II. RECEIVER ARCHITECTURE
III. CIRCUITS AND ANALYSIS
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (22)
참고문헌 신청
S. B. Ferreira, F. Kuo, M. Babaie, S. Bampi, and R. B. Staszewski, “System Design of a 2.75-mW Discrete-Time Superheterodyne Receiver for Bluetooth Low Energy,” IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 5, pp. 1904-1913, May, 2017.
M. Tohidian, I. Madadi, and R. B. Staszewski, “A Fully Integrated Discrete-Time Superheterodyne Receiver,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 635- 647, Feb., 2017.
I. Madadi, M. Tohidian, K. Cornelissens, P. Vandenameele, and R. B. Staszewski, “A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection,” IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 332- 347,Feb., 2016.
Q. Gu, “RF System Design of Transceivers for Wireless Communications,” Springer US, 2005.
F.-J. Huang and K. O, “0.5-μm CMOS T/R switch for 900-MHz wireless applications,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 486?492, Mar., 2001.
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Design of Low-Power Variable Gain Amplifier
제어로봇시스템학회 논문지
2022 .01
-
65 nm CMOS 위상 배열 시스템을 위한 20 dB의 가변 이득 범위를 갖는 조정 캐스코드 가변 이득 증폭기
공학기술논문지
2022 .09
-
무선 중계기용 저전력, 고선형 Up-down Converter
전기학회논문지
2015 .03
-
Design of K-Band CMOS Variable Gain Amplifier Using Amplification Stage and Variable Attenuation Stage
IDEC Journal of Integrated Circuits and Systems
2024 .01
-
A CMOS Dual-mode High-dynamic-range Wideband Receiver RF Front-end
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2018 .10
-
Attenuation Measurement Using the IF Substitution Method in the Frequency Range of 9 kHz to 10 MHz
Journal of Electromagnetic Engineering And Science
2024 .07
-
An Ultra Low-power Low-noise Neural Recording Analog Front-end IC for Implantable Devices
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2018 .08
-
차량용 레이더를 위한 26GHz 40nm CMOS 광대역 가변 이득 증폭기 설계
전기전자학회논문지
2018 .06
-
65nm CMOS공정을 이용한 FMCW 레이더 및 라디오미터 일체형 센서용 광대역 IF 가변 이득 증폭기
전자공학회논문지
2018 .10
-
A New Third-Order Harmonic Mixer Design for Microwave Radar
한국전자통신학회 논문지
2020 .01
-
10-GHz band 2X2 phased-array radio frequency receiver with 8-bit linear phase control and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology
[ETRI] ETRI Journal
2024 .08
-
압축 센싱 수신기용 광대역 전단부 집적화 설계
전자공학회논문지
2018 .04
-
2차 고조파 최소화를 위한 광대역 중간주파수신기 개발
한국전자파학회논문지
2022 .01
-
A 6.1-to-41.5 GHz CMOS Low-Noise Amplifier for Wideband and Highly Linear Applications
Journal of Electromagnetic Engineering And Science
2025 .03
-
Design of Low Noise Amplifier Utilizing Input and Inter Stage Matching Circuits
한국정보통신학회논문지
2021 .06
-
An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .10
-
A 3.6V Rail-to-Rail Operational Amplifier with Constant gm
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2015 .06
-
Design of a wireless transceiver in 0.18um CMOS technology for LoRa application
IDEC Journal of Integrated Circuits and Systems
2018 .07
-
A Design of Wideband Single to Differential Low Noise Amplifier with Automatic Mismatch Calibration
대한전자공학회 학술대회
2015 .06
-
A 1Gbps reference-less clock and data recovery using injection phase locked loop
IDEC Journal of Integrated Circuits and Systems
2018 .07
이 논문의 저자 정보
이 논문과 함께 이용한 논문
A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS
Dongmin Kim
,
Donggu Im
,
In-Young Lee
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2019
.10
Development of Train Regenerative Braking Ground Absorbing Device Based on Super Capacitor Energy Storage
LI Kunpeng
,
LIU Wei
,
LI Qunzhan
외 5명
ICPE(ISPE)논문집
2019
.05
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2018-569-003336544