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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.1
- 발행연도
- 2015.2
- 수록면
- 41 - 47 (7page)
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In this paper, the effective electron Schottky barrier height (Ф<SUB>Bn</SUB>) of the Ni silicide/nsilicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 ㎚). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective Ф<SUB>Bn</SUB> is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 ㎚) and Sb/Ni/TiN (10/15/10 ㎚) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective Ф<SUB>Bn</SUB> of 0.076 eV was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 ㎚) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. EXPERIMENT
Ⅲ. RESULTS AND DISCUSSION
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
1. [학술대회논문] - H. Noda / 1993 / Threshold Voltage Controlled 0.1- μm MOSFET Utilizing Inversion Layer as Extreme Shallow Source/Drain / IEEE International Electron Devices Meeting : 123 ~ 126
2. [학술대회논문] - A. Amerasekera / 1996 / Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 μm CMOS Process / IEEE International Electron Devices Meeting : 893 ~ 896
3. [학술지(정기간행물)] - S. D. Kim / 2002 / Advanced model and analysis of series resistance for CMOS scaling into nanometer regime / IEEE Transactions on Electron Devices 49 (3) : 467 ~ 472
4. [학술대회논문] - S. Shishiguchi / 1997 / Boron Implanted Shallow Junction Formation by High-Temperature/ Short- Time/High-Ramping-Rate(400oC/sec) RTA / Symposium on VLSI Technology : 89 ~ 90
5. [학술대회논문] - R. T. P. Lee / 2006 / Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub- 35nm Gate Length / IEEE International Electron Devices Meeting : 1 ~ 4
2. [학술대회논문] - A. Amerasekera / 1996 / Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 μm CMOS Process / IEEE International Electron Devices Meeting : 893 ~ 896
3. [학술지(정기간행물)] - S. D. Kim / 2002 / Advanced model and analysis of series resistance for CMOS scaling into nanometer regime / IEEE Transactions on Electron Devices 49 (3) : 467 ~ 472
4. [학술대회논문] - S. Shishiguchi / 1997 / Boron Implanted Shallow Junction Formation by High-Temperature/ Short- Time/High-Ramping-Rate(400oC/sec) RTA / Symposium on VLSI Technology : 89 ~ 90
5. [학술대회논문] - R. T. P. Lee / 2006 / Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub- 35nm Gate Length / IEEE International Electron Devices Meeting : 1 ~ 4
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