지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 193 - 196 (4page)
이용수
초록· 키워드
오류제보하기
In this paper we proposed a partially-parallel decoder for irregular LDPC codes from IEEE802.11n standards. Our proposed decoder adopts high-efficiency message-passing algorithm and uses the min-sum algorithm handle the message-passing to reduce the hardware implementation complexity and area, and keep high throughput. Considering reducing the power consumption, we used half-registers and half-memory to store the temporary intrinsic messages. The wasted motion of shiftregister was suppressed. This strategy would save us higher as 30% power under good channel condition. The synthesis result in TSMC 0.18um COMS technology demonstrated that for (1296,324) irregular LDPC code achieved high throughput (1.05Gbps) at the frequency of 200㎒, with 6% area reduction.
목차
Abstract
1. Introduction
2. Min-Sum algorithm
3. High-efficiency message-passing algorithm
4. A compressing method for data store
5. Hardware architecture
6. Implementation result
7. Conclusion
8. Acknowledgement
References
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Irregular Low-Density Parity-Check Code Decoder Using Message-Passing Algorithm
한국통신학회 학술대회논문집
2001 .11
-
A Study Into High-Throughput Decoder Architectures For High-Rate LDPC Codes
대한전자공학회 ISOCC
2012 .11
-
An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .12
-
IEEE 802.16e WiMAX용 (576,288) LDPC 복호기 설계
대한전자공학회 학술대회
2011 .06
-
Efficient Forced Convergence Algorithm for Low Power LDPC Decoders
대한전자공학회 ISOCC
2013 .11
-
Power-Aware Message Processing Unit Design for Fast LDPC Decoder
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2005 .07
-
A Hard Decision LDPC Decoder Implementation for Error Correction of NAND Flash Memory
ICEIC : International Conference on Electronics, Informations and Communications
2008 .06
-
Low Complexity Full Parallel Multi-Split LDPC Decoder Reusing Sign Wire of Row Processor
대한전자공학회 ISOCC
2012 .11
-
A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2012 .03
-
Memory Efficient Decoder Design of Nonbinary LDPC Codes
대한전자공학회 ISOCC
2011 .11
-
An Efficient Implementation of LDPC Decoder with Partial Parallel Algorithm for DVB-S2 System
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2008 .07
-
Min-Sum 알고리즘 기반 LDPC 복호화기를 위한 저전력 갱신생략 방법
대한전자공학회 학술대회
2014 .06
-
IEEE 802.11n 무선 랜 표준용 LDPC 복호기 설계
전자공학회논문지-SD
2010 .05
-
IEEE 802.16e WiMAX용 (2304,1152) LDPC 복호기 설계
대한전자공학회 학술대회
2010 .11
-
1.4 Gbps 비이진 LDPC 코드 복호기를 위한 Fully-Parallel 아키텍처
전자공학회논문지
2016 .04
-
New Message-Passing Decoding Algorithm of LDPC Codes by Partitioning Check Nodes
한국통신학회 학술대회 및 강연회
2005 .04
-
An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2013 .02
-
Simplified 2-Dimensional Scaled Min-Sum Algorithm for LDPC Decoder
Journal of Electrical Engineering & Technology
2017 .05
-
Complexity-Reduced Algorithms for LDPC Decoder for DVB-S2 Systems
[ETRI] ETRI Journal
2005 .10
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001139001