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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.1
- 발행연도
- 2013.2
- 수록면
- 8 - 14 (7page)
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초록· 키워드
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A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon"s limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dualdiagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional nonoverlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.
목차
Abstract
I. INTRODUCTION
II. THE SUM-PRODUCT ALGORITHM AND DUAL-DIAGONAL QUASI-CYCLIC STRUCTURE
III. THE OVERLAPPED (UPPER) DUALDIAGONALLDPC DECODER
IV. THE EXPERIMENT RESULTS
V. CONCLUSION
REFERENCES
참고문헌 (20)
참고문헌 신청
S. Jeon / 2010 / Performance and Complexity of 32 k-bit Binary LDPC Codes for Magnetic Recording Channels / IEEE Trans. Magnetics 46:2244~2247
H. Zhong / 2007 / Quasi- Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation / IEEE Trans. Magnetics 43:1118~1123
M. P. C. Fossorier / 2004 / Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Matrices / IEEE Trans. Info. Theory 50:1788~1793
M. Jiang / 2010 / An improved variable length coding scheme using structured LDPC codes / IEEE Int. Conf. on WCSP
Z. Wang / 2011 / VLSI Design for Low-Density Parity-Check Code Decoding / IEEE Circuit and System Mag. 11:52~69
H. Zhong / 2007 / Quasi- Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation / IEEE Trans. Magnetics 43:1118~1123
M. P. C. Fossorier / 2004 / Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Matrices / IEEE Trans. Info. Theory 50:1788~1793
M. Jiang / 2010 / An improved variable length coding scheme using structured LDPC codes / IEEE Int. Conf. on WCSP
Z. Wang / 2011 / VLSI Design for Low-Density Parity-Check Code Decoding / IEEE Circuit and System Mag. 11:52~69
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