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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2024.11
- 수록면
- 448 - 451 (4page)
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초록· 키워드
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In this paper, we present a low-power Phase Locked Loop (PLL) designed for Internet of Things (IoT) applications, addressing the growing demand for low-power wireless technologies, low noise characteristics, and high reception sensitivity. The proposed PLL operates with a 1V supply, consuming 1mA of current and 1mW of power. It functions as a frequency synthesizer capable of generating Local Oscillator (LO) signals at 262MHz, 433MHz, 868MHz, and 920MHz, which are key frequencies for IoT communications.
The PLL features an analog architecture, including a Phase Frequency Detector (PFD), Charge Pump (CP), Voltage-Controlled Oscillator (VCO), and a 3rd-order internal loop filter. Measurement results show -87.3 dBc/Hz at 100kHz and -101 dBc/Hz at a 1MHz offset. The design utilizes a 60nm CMOS process and occupies an area of 850μm x 1200μm.
The PLL features an analog architecture, including a Phase Frequency Detector (PFD), Charge Pump (CP), Voltage-Controlled Oscillator (VCO), and a 3rd-order internal loop filter. Measurement results show -87.3 dBc/Hz at 100kHz and -101 dBc/Hz at a 1MHz offset. The design utilizes a 60nm CMOS process and occupies an area of 850μm x 1200μm.
목차
Abstract
I. 서론
II. 본론
III. 구현
Ⅳ. 결론 및 향후 연구 방향
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