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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.3
- 발행연도
- 2024.6
- 수록면
- 249 - 258 (10page)
- DOI
- 10.5573/JSTS.2024.24.3.249
이용수
초록· 키워드
오류제보하기
The double diffused drain N-type MOS (DDDNMOS) transistor with a dipolar source is proposed to realize stable and robust electrostatic discharge (ESD) protection performance. The proposed dipolar source is a structure in which a P<SUP>+</SUP> diffusion layer is intentionally inserted on the side of the N<SUP>+</SUP> source to prevent lateral diffusion of the electron-rich region from the N+ source. According to the 2D simulation and measured TLP results, it was found that the inserted P<SUP>+</SUP> diffusion layer effectively prevented the formation of deep electron channels caused by electron injection. Therefore, the double snapback phenomenon, which is a problem in the conventional DDDNMOS standard device, can be solved.
목차
Abstract
I. INTRODUCTION
II. DETERMINATION OF DESIGN PARAMETERS
III. DEVICE STRUCTURES AND ANALYSIS METHOD
IV. RESULTS AND DISCUSSION
V. CONCLUSIONS
REFERENCES
참고문헌 (17)
참고문헌 신청
Y. J. Seo and K. H. Kim, “Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device,” Microelectronic Engineering, Vol. 84, No. 1, p. 161-164, 2007.
Byung-Seok Lee and Yong-Seo Koo, “SCR-based ESD Protection Circuit with Low Trigger Voltage and High Robustness by Inserting the NMOS Structure,” Journal of semiconductor Technology and Science, Vol. 19, No. 3, June, 2019.
Kyoung-Il Do and Yong-Seo Koo, “A Design of Whole-chip ESD Protection Circuit with SCR-based I/O and LIGBT-based Power Clamp,” Journal of semiconductor Technology and Science, Vol. 21, No. 1, Feb., 2021.
G. Bosselli, S. Meeuwsen, T. Mouthaan and F. Kuper, “Investigations on double diffused MOS (DMOS) transistors under ESD zap conditions,” in Proc. EOS/ESD Symp., pp. 11-18, 1999.
M. P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker and W. Fichtner, “Analysis of lateral DMOS power devices under ESD stress conditions,” IEEE Trans. Electron Devices, 47, pp. 2128-2137, 2000.
Byung-Seok Lee and Yong-Seo Koo, “SCR-based ESD Protection Circuit with Low Trigger Voltage and High Robustness by Inserting the NMOS Structure,” Journal of semiconductor Technology and Science, Vol. 19, No. 3, June, 2019.
Kyoung-Il Do and Yong-Seo Koo, “A Design of Whole-chip ESD Protection Circuit with SCR-based I/O and LIGBT-based Power Clamp,” Journal of semiconductor Technology and Science, Vol. 21, No. 1, Feb., 2021.
G. Bosselli, S. Meeuwsen, T. Mouthaan and F. Kuper, “Investigations on double diffused MOS (DMOS) transistors under ESD zap conditions,” in Proc. EOS/ESD Symp., pp. 11-18, 1999.
M. P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker and W. Fichtner, “Analysis of lateral DMOS power devices under ESD stress conditions,” IEEE Trans. Electron Devices, 47, pp. 2128-2137, 2000.
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