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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2023.6
- 수록면
- 62 - 66 (5page)
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초록· 키워드
오류제보하기
This paper describes a low-jitter and highfrequency ring-oscillator (RO)-based multiplying delay locked loop (MDLL). The proposed MDLL uses a power-gating (PG) technique to periodically turn on and off the RO and remove the accumulated jitter. By using the technique, the proposed MDLL can overcome the limit of conventional MDLLs that use a series MUX for edge switching. Therefore, the proposed MDLL can achieve a very low jitter even at a very high output frequency above 10GHz with a large multiplication factor (N) over 100. The measured rms jitter was 122fs and reference spur was -60dBc at 12.24GHz (N=102).
목차
Abstract
Ⅰ. Introduction
Ⅱ. Proposed PG-MDLL
Ⅲ. Measurement
Ⅳ. Conclusion
References
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