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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.1
- 발행연도
- 2022.2
- 수록면
- 1 - 9 (9page)
- DOI
- 10.5573/JSTS.2022.22.1.1
이용수
초록· 키워드
오류제보하기
A leadless surface mount package was developed to enhance the switching and heat-dissipation properties of a power semiconductor. The package was implemented through a low-temperature co-fired ceramic (LTCC)-based multilayer circuit substrate that could form embedded cavities. A silicon carbide (SiC) Schottky barrier diode (SBD) bare die was attached to the cavity in the LTCC substrate. Chip interconnection was realized using a wide and thick copper (Cu) clip with a low parasitic inductance and electrical resistance compared to those of a conventional wire. Silver-filled multiple vias and wide metal planes were used to reduce the electrical parasitic effects and enhance the heat-dissipation of the package. The DC and dynamic characteristics of the 600 V/10 A-class SiC SBD package involving the proposed technologies were evaluated. The dynamic test results indicated that the reverse recovery charge (Qrr) was 18.7% lower than that of a traditional TO-220 packaged product with the same bare die. Furthermore, two leadless commercial products and he proposed package prototype were applied to a power factor correction (PFC) converter, and the power loss and heat-dissipation performances were compared. The proposed package exhibited a lower loss and higher heat dissipation than those of the commercial products.
목차
Abstract
I. INTRODUCTION
II. PROPOSED PACKAGE
III. PFC CONVERTER INCLUDING THE PROPOSED PACKAGE
V. CONCLUSIONS
REFERENCES
참고문헌 (20)
참고문헌 신청
T. Liu, T. T. Y. Wong, and Z. J. Shen, “A survey on switching oscillations in power converters,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 8, No. 1, pp. 893-908, Mar., 2020.
T. Meade, et al., “Parasitic inductance effect on switching losses for a high frequency dc-dc converter,” Appl. Power Electron. Conf. Expo., Austin, TX, USA, pp. 3-9, Feb., 2008.
F. Yang, et al., “Electrical performance advancement in SiC power module package design with Kelvin drain connection and low parasitic inductance,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 7, No. 1, pp. 84-98, Mar., 2019.
D. Y. Jung, et al., “Power semiconductor SMD package embedded in multilayered ceramic for low switching loss,” ETRI J., Vol. 39, No. 6, pp. 866-873, Dec., 2017.
S. Li, et al., “Stray inductance reduction of commutation loop in the P-cell and N-cell-based IGBT phase leg module,” IEEE Trans. Power Electron., Vol. 29, No. 7, pp. 3616-3624, July 2014.
T. Meade, et al., “Parasitic inductance effect on switching losses for a high frequency dc-dc converter,” Appl. Power Electron. Conf. Expo., Austin, TX, USA, pp. 3-9, Feb., 2008.
F. Yang, et al., “Electrical performance advancement in SiC power module package design with Kelvin drain connection and low parasitic inductance,” IEEE J. Emerg. Sel. Topics Power Electron., Vol. 7, No. 1, pp. 84-98, Mar., 2019.
D. Y. Jung, et al., “Power semiconductor SMD package embedded in multilayered ceramic for low switching loss,” ETRI J., Vol. 39, No. 6, pp. 866-873, Dec., 2017.
S. Li, et al., “Stray inductance reduction of commutation loop in the P-cell and N-cell-based IGBT phase leg module,” IEEE Trans. Power Electron., Vol. 29, No. 7, pp. 3616-3624, July 2014.
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