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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.5
- 발행연도
- 2019.10
- 수록면
- 435 - 445 (11page)
- DOI
- 10.5573/JSTS.2019.19.5.435
이용수
초록· 키워드
오류제보하기
Many modern applications, such as object recognition using deep neural networks, require extremely large numbers of multiplications, but can sacrifice accuracy in order to achieve lower power usage and faster operation. This paper proposes a new approximate multiplier design based on radix-4 Booth encoding. The key novel aspect of the proposed design is that approximate circuits are designed to create intermediate terms, which are then used as the common inputs to almost all of the logic within one entire row of a partial product array, resulting in a multi-level logic circuit implementation with extremely low delay and power usage characteristics. The proposed 8-bit (16-bit) design improves the power delay product by 17.1% to 30.3% (88.9% to 96.4%) over the previous best designs. By using accurate, approximated, and truncated regions, a wide range of approximate multiplier designs with different error characteristics are possible. Using normalized mean error distance and relative error distance metrics, simulations using synthesized circuits are used to show that the proposed designs have significantly improved power/accuracy tradeoffs over the previous best designs.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PRELIMINARIES
Ⅲ. PROPOSED DESIGN
Ⅳ. EVALUATION
Ⅴ. CONCLUSION
REFERENCES
참고문헌 (16)
참고문헌 신청
Q. Xu, T. Mytkowicz, and N. S. Kim, “Approximate computing: A survey,” IEEE Design & Test, vol. 33, no. 1, pp. 8?22, 2016.
W. Liu, L. Qian, C. Wang, H. Jiang, J. Han, and F. Lombardi, “Design of approximate radix-4 booth multipliers for error-tolerant computing,” IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435?1441, 2017.
Z. Zhang and Y. He, “A low error energy-efficient fixed-width booth multiplier with sign-digit-based conditional probability estimation,” IEEE Transactions on Circuits and Systems II, Express Briefs, 2017.
C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, “A probabilistic estimation bias circuit for fixedwidth booth multiplier and its dct applications,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 58, no. 4, pp. 215?219, 2011.
T.-B. Juang and S.-F. Hsiao, “Low-error carry-free fixed-width multipliers with low-cost compensation circuits,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 52, no. 6, pp. 299? 303, 2005.
W. Liu, L. Qian, C. Wang, H. Jiang, J. Han, and F. Lombardi, “Design of approximate radix-4 booth multipliers for error-tolerant computing,” IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435?1441, 2017.
Z. Zhang and Y. He, “A low error energy-efficient fixed-width booth multiplier with sign-digit-based conditional probability estimation,” IEEE Transactions on Circuits and Systems II, Express Briefs, 2017.
C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, “A probabilistic estimation bias circuit for fixedwidth booth multiplier and its dct applications,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 58, no. 4, pp. 215?219, 2011.
T.-B. Juang and S.-F. Hsiao, “Low-error carry-free fixed-width multipliers with low-cost compensation circuits,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 52, no. 6, pp. 299? 303, 2005.
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