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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 484 - 487 (4page)
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초록· 키워드
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In this paper, we propose a RT level power reduction scheme which can be used for the applications that require ultra-low power consumption. A novel wasting-toggle-rate (WTR) based clock power reduction technique is introduced. It compares the WTR of a stimulus with the pre-computed threshold WTR of the circuit, and clock gating is applied to the circuit only if there is power-saving benefit. It considers not only clock enable signal, but also data signal and wasting toggle rate of the clock in a finegrained manner. The proposed technique is implemented at RT level in a complete CAD solution. We have tested the proposed technique on real industrial multimedia-mobile-processor design. For the accuracy of the power optimization results, all the power estimation results are measured at gate level after synthesis by using industrial 65 and 90 nanometer technology libraries. The experimental results show that using 65 nanometer technology, the technique reduces 35.46% power comparing with nonclock gating design and 18.80% power comparing with clockgating design by Power Compiler; and that using 90 nanometer technology, the technique reduces average 39.34% total power comparing with non-clock gating design and 27.76% total power comparing with clock-gating design by Power Compiler. For the design overhead of the proposed technique, it increases 1.17% of the critical path delay and reduces 0.81% of the area for the whole circuit comparing with the original circuit in 65 nanometer technology, and increases 2.75% of the critical path delay and reduces 0.75% area for whole circuit in 90 nanometer technology.
목차
Abstract
I. INTRODUCTION
II. PRELIMINARIES
III. TWTR-BASED CLOCK GATING
IV. POWER-OPTIMIZED CODE GENERATION
V. EXPERIMENTAL RESULTS
VI. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001483304