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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 1,101 - 1,104 (4page)
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초록· 키워드
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The AMBA AHB has been popular bus architecture so far due to its simple architecture. Complex system-on-chips (SoCs) with multiple masters usually employ bus architecture with multiple layers or multiple channels because they require large bandwidth. We construct four systems with different bus configuration to analyze and compare the performance of shared buses and on-chip-network with multiple channels. The systems include multiple masters in parallel processing. The shared bus architecture with multiple layers provides less bandwidth than expected and the on-chip-networks with independent multiple channels show better performance. The system with multiple channels shows 2-3 times better performance than that with the AHB. The results are verified by simulation and implementation using an FPGA.
목차
Abstract
1. Introduction
2. Bus and On-Chip-Network Architecture
3. Simulation and Verification
4. Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2013-569-001141270