지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE JOUNAL OF SEMICONDUCTOR THCHNOLOGY AND SCIENCE Vol.4 No.4
- 발행연도
- 2004.12
- 수록면
- 286 - 292 (7page)
이용수
이 논문의 연구 히스토리 (2)
- 이 논문의 후속연구가 궁금하신가요?
- 연관 학술논문 또는 학술발표를 통해 보다 발전된 연구결과를 확인하실 수 있습니다.
- 이 논문의 연구 히스토리 확인하기
초록· 키워드
오류제보하기
In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which function blocks are mapped. To apply it to multitask applications, the concurrent execution of the function blocks of different tasks also should be considered. Since tasks are scheduled independently, considering all cases of concurrency in each processing element is impractical. Therefore we make an average estimate on the effects of other tasks with respect to bus request rate and bus access time. The proposed technique was incorporated with our exploration framework for on-chip bus architectures. Its viability and efficiency are validated by a preliminary example.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. RELATED WORK
Ⅲ. REVIEW ON EXPLORATION FLOW
Ⅳ. ESTIMATION OF MULTITASK APPLICATIONS
Ⅴ. EXPERIMENTS
Ⅵ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
저자소개
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Exploring On-Chip Bus Architectures for Multi-Task Applications
대한전자공학회 ISOCC
2004 .10
-
Novel Segmented Bus Architecture Suitable to Multitasking for MPEG4 Chip
대한전자공학회 ISOCC
2004 .10
-
The Proposed On-Chip Bus System with GALDS Topology
대한전자공학회 ISOCC
2008 .11
-
A Bus Data Compression Method on a Phase-Based On-Chip Bus
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2012 .06
-
A High-Performance On-Chip Bus Architecture Design
대한전자공학회 학술대회
2016 .04
-
A High-Performance On-Chip Bus Architecture Design
정보 및 제어 논문집
2016 .04
-
MPEG 시스템용 다중 작업에 적합한 양방향 버스 구조
전자공학회논문지-SD
2005 .04
-
A Novel High Performance Bus Topology for Parallel Processing in MPSoC
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2009 .07
-
Incommensurate structure and x-ray pow-der diffraction data for $Bi_2Sr_2Ca_2Cu_2O_{8+x}$(Bi-2212 phase) and $Bi_2Sr_2Ca_2Cu_3O_{10+x}$(Bi-2223 phase)
한국재료학회 학술발표대회
1992 .01
-
M-BUS(Metropolitan Bus) 서비스개선 방향제시
대한산업공학회 추계학술대회 논문집
2013 .11
-
차량 이동궤적 기반 버스정차대 기하구조 연구
한국도로학회논문집
2015 .01
-
Design of a High-Performance On-Chip Bus
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2016 .06
-
Bi$_2O_3$유리조성계와 전극과의 반응 평가
한국재료학회 학술발표대회
2005 .01
-
An Analysis of On-Chip-Network Communication Properties on Shared and Multiple Channel Architecture
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2008 .07
-
High Performance On-Chip-Network Architecture with Multiple Channels and Dual Routing
대한전자공학회 ISOCC
2008 .11
-
Bus System Engineering
한국통신학회 세미나
1990 .01
-
Works - bi-house
건축사
2019 .01
-
Active Bus Teminater for High-Speed Off-Chip Bus
대한전자공학회 학술대회
1995 .01
-
B2Bi 구현사례 및 솔루션 개발
대한산업공학회 춘계공동학술대회 논문집
2002 .05
-
THERMAL ANALYSIS ON POLYMORPHISMS OF Bi203 AND Bi12SiO20
KSME/JSME THERMAL and FLUID Engineering Conference
1996 .10
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2009-569-014416778