지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 314 - 317 (4page)
이용수
초록· 키워드
오류제보하기
New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, it induces significant complexity increase. In this paper, an efficient architecture for spiral-type ME is proposed. First, we propose a hardware-friendly spiral search order. Then, an improved processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables the shift of the reference pixel data to top, bottom, right, and left by four input and output ports. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4×4 is introduced in the proposed architecture. As a result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134㎒ in the case of FPGA(Xilinx Vertex5) implementation.
목차
Abstract
1. Introduction
2. Spiral-Type Motion Estimation
3. Proposed ME Architecture
4. Implementation Results
5. Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2012-569-004020447