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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 540 - 543 (4page)
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초록· 키워드
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In this paper, we present a new motion estimation hardware architecture using a sub-sampled block, which can be used for frame rate up-conversion. The proposed architecture provides the advantage of reducing computational hardware complexity greatly, compared to the conventional architecture, while maintaining the quality of interpolated images. FPGA implementation shows that the proposed motion estimation hardware architecture reduces the hardware size by 51 %, compared to the conventional architecture at the cost of average PSNR degradation of only 0.22bB for interpolated images.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED MOTION ESTIMATION METHOD
Ⅲ. EXPERIMENTAL RESULTS
Ⅳ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001759470